wm8594seft-v Wolfson Microelectronics plc, wm8594seft-v Datasheet
wm8594seft-v
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wm8594seft-v Summary of contents
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... DVD-RW http://www.wolfsonmicro.com/enews/ WM8594 DAC: 100dB SNR typical (‘A’ weighted @ 48kHz) DAC: -87dB THD typical ADC: 96dB SNR typical (‘A’ weighted @ 48kHz) ADC: -80dB THD typical LJ, RJ, DSP Production Data, July 2008, Rev 4.1 Copyright ©2008 Wolfson Microelectronics plc ...
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WM8594 BLOCK DIAGRAM Stereo ADC ADC Input Mux VIN1L VIN1R VIN2L VIN2R VIN3L VIN3R VIN4L VIN4R VIN5L VIN5R w WM8594 w Control Interface Audio Interface Volume Control Matrix Channel Digital Volume Control Filters Volume Control Matrix Channel PGA1L PGA1R PGA ...
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Production Data DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................2 PIN CONFIGURATION...........................................................................................4 ORDERING INFORMATION ..................................................................................4 PIN DESCRIPTION ................................................................................................5 ABSOLUTE MAXIMUM RATINGS.........................................................................6 THERMAL PERFORMANCE .................................................................................6 RECOMMENDED OPERATING CONDITIONS .....................................................7 SUPPLY CURRENT CONSUMPTION ...................................................................7 ELECTRICAL CHARACTERISTICS ......................................................................8 TERMINOLOGY .......................................................................................................... 10 MASTER CLOCK ...
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... WM8594 PIN CONFIGURATION ORDERING INFORMATION TEMPERATURE DEVICE RANGE o WM8594SEFT/V - WM8594SEFT/RV -40 to +85 C Note: Reel quantity = 2,200 w MOISTURE SENSITIVITY PACKAGE 48-lead TQFP (Pb-free) 48-lead TQFP (Pb-free, tape and reel) Production Data PEAK SOLDERING LEVEL TEMPERATURE MSL3 260˚C MSL3 260˚C PD Rev 4 ...
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Production Data PIN DESCRIPTION PIN NAME 1 ADCLRC Digital Input/Output 2 ADCBCLK Digital Input/Output 3 DOUT Digital Output 4 DACMCLK1 5 DACLRC1 6 DACBCLK1 7 DIN1 8 DACMCLK2 9 DACLRC2 10 DACBCLK2 11 DIN2 12 DVDD 13 DGND 14 /PWDN ...
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WM8594 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics ...
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Production Data RECOMMENDED OPERATING CONDITIONS PARAMETER Digital power supply Analogue power supply Analogue power supply Ground DGND/AGND1/ Operating temperature range Notes: 1. Digital supply (DVDD) must never be more than 0.3V greater than AVDD1 in normal operation. 2. Digital ground ...
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WM8594 ELECTRICAL CHARACTERISTICS Test Conditions AVDD2=9V, AVDD1=DVDD=3.3V, AGND1=AGND2=0V, DGND=0V, TA=+25˚C, 1kHz signal, fs=48kHz, MCLK=256fs unless otherwise stated PARAMETER Digital logic levels Input low level Input high level Output low level Output high level Digital input leakage current Digital input leakage ...
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Production Data Test Conditions AVDD2=9V, AVDD1=DVDD=3.3V, AGND1=AGND2=0V, DGND=0V, TA=+25˚C, 1kHz signal, fs=48kHz, MCLK=256fs unless otherwise stated PARAMETER DAC Performance 1,5 Signal to Noise Ratio 2,5 Dynamic Range 3,5 Total Harmonic Distortion 4,5 Channel Separation Channel Level Matching Channel Phase Deviation ...
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WM8594 Test Conditions AVDD2=9V, AVDD1=DVDD=3.3V, AGND1=AGND2=0V, DGND=0V, TA=+25˚C, 1kHz signal, fs=48kHz, MCLK=256fs unless otherwise stated PARAMETER Digital Volume Control ADC minimum digital volume ADC maximum digital volume ADC volume step size DAC minimum digital volume DAC maximum digital volume DAC ...
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Production Data Notes: 1. All minimum and maximum values are subject to change. 2. This resistance is selectable using VMID_SEL[1:0] – see Figure 52 for full details. 3. See p77 for details of extended input impedance configuration. MASTER CLOCK TIMING ...
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WM8594 DIGITAL AUDIO INTERFACE TIMING – SLAVE MODE Figure 3 Slave Mode Digital Audio Data Timing Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, T DACMCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER ...
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Production Data DIGITAL AUDIO INTERFACE TIMING – MASTER MODE Figure 4 Master Mode Digital Audio Data Timing Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, T DACMCLK = 256fs, 24-bit data, unless otherwise stated. ...
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WM8594 CONTROL INTERFACE TIMING – 2-WIRE MODE Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, T DACMCLK = 256fs, 24-bit data, unless otherwise stated. ...
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Production Data CONTROL INTERFACE TIMING – 3-WIRE MODE Figure 6 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, T DACMCLK = 256fs, 24-bit data, unless otherwise ...
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WM8594 POWER ON RESET (POR) Figure 1 Power Supply Timing Requirements Test Conditions DVDD = 3.3V, AVDD1 = 3.3V, AVDD2 = 9V DGND = AGND1 = AGND2 = 0V, T AVDD1 = DVDD = 3.63V, AVDD1 max max PARAMETER SYMBOL ...
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Production Data DEVICE DESCRIPTION INTRODUCTION The WM8594 is a high performance multi-channel audio CODEC with 2Vrms line level inputs and outputs and flexible analogue input / output switching. The device comprises a 24-bit stereo ADC, two 24-bit stereo DACs with ...
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WM8594 CONTROL INTERFACE Control of the WM8594 is achieved by a 2-wire SM-bus-compliant or 3-wire SPI compliant serial interface with readback. Software interface mode is selected using the MODE pin as shown in Table 8 below: Table 8 Control Interface ...
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Production Data AUTO-INCREMENT REGISTER WRITE It is possible to write to multiple consecutive registers using the auto-increment feature. When AUTO_INC is set, the register write protocol follows the method shown in Figure 8. As with normal register writes, the controller ...
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WM8594 3-WIRE (SPI COMPATIBLE) SERIAL CONTROL INTERFACE MODE REGISTER WRITE SDIN is used for the program data, SCLK is used to clock in the program data and /CS is use to latch in the program data. SDIN is sampled on ...
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Production Data DEVICE ID AND REVISION Reading from register R0 returns the device ID. Reading from register R1 returns the device revision number. REGISTER ADDRESS R0 DEVICE_ID 00h R1 REVISION 01h Table 10 Device ID and Revision Number DIGITAL AUDIO ...
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WM8594 I2S MODE mode, the MSB of input data is sampled on the second rising edge of bit clock following a left/right clock transition. The MSB of output data changes on the first falling edge of ...
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Production Data RIGHT JUSTIFIED (RJ) MODE In RJ mode the LSB of input data is sampled on the rising edge of bit clock preceding a left/right clock transition. The LSB of output data changes on the falling edge of bit ...
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WM8594 DSP MODE B In DSP Mode B, the MSB of channel 1 left data input is sampled on the first bit clock rising edge following a left/right clock rising edge. Channel 1 right data then follows. The MSB of ...
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Production Data REGISTER ADDRESS R7 DAC2_CTRL1 07h R13 ADC_CTRL1 0Dh Table 11 Audio Interface Control w BIT LABEL DEFAULT 5 DAC1_LRP 0 DAC1 LRCLK Polarity 0 = DACLRCLK not inverted 1 = DACLRCLK inverted 1:0 DAC2_ 10 DAC2 Audio Interface ...
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WM8594 DIGITAL AUDIO INTERFACE Digital audio data is transferred to and from the WM8594 via the digital audio interface. The DACs have independent data inputs and master clocks, bit clocks and left/right frame clocks, and operate in both master or ...
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Production Data REGISTER ADDRESS R8 DAC1_CTRL2 08h R9 DAC2_CTRL3 09h R14 ADC_CTRL2 0Eh R15 ADC_CTRL3 0Fh Table 12 ADC Master Mode Control w BIT LABEL DEFAULT 2:0 DAC2_ 000 DAC MCLK:LRCLK Ratio SR[2:0] 000 = Auto detect 001 = 128fs ...
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WM8594 SLAVE MODE In slave mode, the master clock to left/right clock ratio can be auto-detected or set manually by register write. REGISTER ADDRESS R3 DAC1_CTRL2 03h R8 DAC2_CTRL2 08h R14 ADC_CTRL2 0Eh Table 13 Slave Mode MCLK to LRCLK ...
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Production Data DIGITAL AUDIO DATA SAMPLING RATES In a typical digital audio system there is one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio ...
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WM8594 DAC FEATURES The WM8594 includes two 24-bit DACs with independent clocks and independent data inputs. The DACs include digital volume control with zero cross and soft mute, de-emphasis support, and the capability to select the output channels to be ...
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Production Data REGISTER ADDRESS R2 DAC1_CTRL1 02h R7 DAC2_CTRL1 07h Table 17 DAC Digital Volume Control SOFTMUTE A soft mute can be applied to DAC1 and DAC2 independently. REGISTER ADDRESS R2 DAC1_CTRL1 02h R7 DAC2_CTRL1 07h Table 18 DAC Softmute ...
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WM8594 DIGITAL MONOMIX CONTROL Each DAC can be independently set to output a range of mono and stereo options. Each DAC output channel can output left channel data, right channel data or a mix of left and right channel data. ...
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Production Data ADC FEATURES The WM8594 features a stereo 24-bit sigma-delta ADC, digital volume control with zero cross, a selectable high pass filter to remove DC offsets, and support for both master and slave clocking modes. REGISTER ADDRESS R13 ADC_CTRL1 ...
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WM8594 CHANNEL SWAP AND INVERSION The WM8594 ADC input channels can be inverted and swapped in a number of ways to provide maximum flexibility of input path to the ADC. The default configuration provides stereo output data with the left ...
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Production Data ANALOGUE ROUTING CONTROL The WM8594 has a number of analogue paths, allowing flexible routing of a number of analogue input signals and DAC output signals at levels up to 2Vrms. The analogue paths include volume control with zero ...
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WM8594 REGISTER ADDRESS R19 PGA1L_VOL 13h R20 PGA1R_VOL 14h R21 PGA2L_VOL 15h R22 PGA2R_VOL 16h R23 PGA3L_VOL 17h R24 PGA3R_VOL 18h R19 PGA1L_VOL 13h R20 PGA1R_VOL 14h R21 PGA2L_VOL 15h R22 PGA2R_VOL 16h R23 PGA3L_VOL 17h R24 PGA3R_VOL 18h R25 ...
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Production Data VOLUME RAMP Analogue volume can be adjusted by step change or by soft ramp. The ramp rate is dependent upon the sampling rate. The sampling rate upon which the volume ramp rate is based can be selected between ...
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WM8594 REGISTER ADDRESS R25 PGA_CTRL1 19h R27 ADD_CTRL1 1Bh R36 PGA_CTRL3 24h Table 28 Analogue Volume Ramp Control w BIT LABEL DEFAULT 0 DECAY_ 0 PGA Gain Decay Mode BYPASS 0 = PGA gain will ramp down 1 = PGA ...
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Production Data ANALOGUE MUTE CONTROL The analogue channel PGAs can be muted independently and are muted by default. Alternatively, all mute bits can be set using a master mute bit, MUTE_ALL. Setting one of these mute bits is equivalent to ...
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WM8594 INPUT SELECTOR CONTROL Each left channel input PGA can select between all left channel analogue inputs, and both left and right DAC inputs. Each right channel input PGA can select between all right channel analogue inputs, and both left ...
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Production Data REGISTER ADDRESS R28 INPUT_CTRL1 1Ch R29 INPUT_CTRL2 1Dh R28 INPUT_CTRL1 1Ch R29 INPUT_CTRL2 1Dh R31 INPUT_CTRL4 1Fh Table 30 PGA Input Select Control w BIT LABEL DEFAULT 3:0 PGA1L_ 0000 Left Input PGA Source Selection IN_ 0000 = ...
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WM8594 ADC INPUT SELECTOR CONTROL The ADC input switch can be configured to allow any combination of two inputs to be input to the ADC. Each input switch channel can be controlled independently. The input switch also includes PGAs to ...
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Production Data OUTPUT SELECTOR CONTROL Any analogue PGA channel can be routed to any analogue output. Care should be taken to ensure that each analogue output is routed to only one analogue input – not possible to route ...
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WM8594 REGISTER ADDRESS R32 OUTPUT_ CTRL1 20h R33 OUTPUT_ CTRL2 21h R34 OUTPUT_ CTRL3 22h Table 32 Output Selection w BIT LABEL DEFAULT 2:0 VOUT1L_ 000 Output Mux Selection SEL[2:0] 000 = PGA1L 5:3 VOUT1R_ 001 001 = PGA1R SEL[2:0] ...
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Production Data POP AND CLICK PERFORMANCE The WM8594 includes a number of features designed to minimise pops and clicks in various phases of operation including power up, power down, changing analogue paths and starting/stopping clocks. In order to ensure optimum ...
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WM8594 POWERDOWN SEQUENCE Power supplies can now be safely removed from the WM8594 if desired. Table 33 describes the various bias control bits for power up/down control. w Mute all PGAs: ...
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Production Data REGISTER ADDRESS R35 BIAS 23h Table 33 Bias Control GLOBAL ENABLE CONTROL The WM8594 includes a number of enable and disable mechanisms to allow the device to be powered on and off in a pop-free manner. A global ...
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WM8594 EMERGENCY POWER DOWN In the event of sudden power failure in a system, or any other emergency condition, the /PWDN pin may be used to power the device down from any state in a controlled manner. This may be ...
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WM8594 R0 (0h) – Software Reset / Device ID Register (DEVICE_ID) Bit # 15 14 Read Write Default 1 0 Bit # 7 6 Read Write Default 1 0 Function Device ID DEVICEID[15:0] A read of this register will return ...
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Production Data R2 (02h) – DAC Control Register 1 (DAC1_CTRL1) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read DAC1_ DAC1_ZCEN DEEMPH Write Default 1 0 Function DAC1 Audio Interface Format ...
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WM8594 R3 (03h) – DAC1 Control Register 2 (DAC1_CTRL2) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read 0 0 Write N/A N/A Default 0 0 Function DAC1 MCLK:LRCLK Ratio DAC1_SR[2:0] ...
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Production Data R5 (05h) – DAC1L Digital Volume Control Register (DAC1L_VOL) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read Write Default 1 1 Function DAC1L_VOL[7:0] DAC1L Digital Volume 0000 0000 ...
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WM8594 R7 (07h) – DAC2 Control Register 1 (DAC2_CTRL1) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read DAC2_ DAC2_ZCEN DEEMPH Write Default 1 0 Function DAC2 Audio Interface Format DAC2_FMT[1:0] ...
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Production Data R8 (08h) – DAC2 Control Register 2 (DAC2_CTRL2) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read 0 0 Write N/A N/A Default 0 0 Function DAC2_SR[2:0] DAC2 MCLK:LRCLK ...
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WM8594 R10 (0Ah) – DAC2L Digital Volume Control Register (DAC2L_VOL) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read Write Default 1 1 Function DAC2L_VOL[7:0] DAC2 Digital Volume 0000 0000 = ...
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Production Data R12 (0Ch) – Device Enable Register (ENABLE) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read 0 0 Write N/A N/A Default 0 0 Function GLOBAL_EN Device Global Enable ...
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WM8594 ADC_EN ADC Enable 0 = ADC disabled 1 = ADC enabled ADC_LRSWAP ADC Left/Right Swap 0 = Normal 1 = Swap left channel data into right channel and vice-versa ADCL and ADCR Output Signal Inversion ADCR_INV ADCL_INV 0 = ...
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Production Data R15 (0Fh) – ADC Control Register 3 (ADC_CTRL3) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read 0 0 Write N/A N/A Default 0 0 Function ADC_MSTR ADC Master ...
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WM8594 R17 (11h) – Right ADC Digital Volume Control Register (ADCR_VOL) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read Write Default 1 1 Function ADCR_VOL[7:0] Right ADC Digital Volume 0000 ...
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Production Data R19 (13h) – PGA1L Volume Control Register (PGA1L_VOL) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read Write Default 0 0 R20 (14h) – PGA1R Volume Control Register (PGA1R_VOL) ...
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WM8594 R23 (17h) – PGA3L Volume Control Register (PGA3L_VOL) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read Write Default 0 0 R24 (18h) – PGA3R Volume Control Register (PGA3R_VOL) Bit ...
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Production Data R25 (19h) – PGA Control Register 1 (PGA_CTRL1) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read PGA3R_ZC PGA3L_ZC Write Default 0 0 Function DECAY_BYPASS PGA Gain Decay Mode ...
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WM8594 R27 (1Bh) – Additional Control Register 1 (ADD_CTRL1) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read 0 Write N/A Default 0 1 Function AUTO_INC 2-wire Software Mode Auto Increment ...
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Production Data R28 (1Ch) – Input Control Register 1 (INPUT_CTRL1) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read PGA1R_IN_SEL[3:0] Write Default 0 0 R29 (1Dh) – Input Control Register 2 ...
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WM8594 R30 (1Eh) – Input Control Register 3 (INPUT_CTRL3) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read ADCR_SEL[3:0] Write Default 1 0 Function ADCL_SEL[3:0] ADC Input Select ADCR_SEL[3:0] 0000 = ...
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Production Data R31 (1Fh) – Input Control Register 4 (INPUT_CTRL4) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read ADCR_AMP_ ADCL_AMP_ EN EN Write Default 0 0 Function PGA1L_EN Input PGA ...
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WM8594 R32 (20h) – Output Control Register 1 (OUTPUT_CTRL1) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read VOUT2L_SEL[1:0] Write Default 1 0 R33 (21h) – Output Control Register 2 (OUTPUT_CTRL2) ...
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Production Data R34 (22h) – Output Control Register 3 (OUTPUT_CTRL3) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read VOUT1L_EN APE_B Write Default 0 1 Function VOUT1L_TRI Output Amplifier Tristate Control ...
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WM8594 R35 (23h) – Bias Control Register (BIAS) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read VMID_SEL[1:0] Write Default 0 0 Function POBCTRL Bias Source for Output Amplifiers 0 = ...
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Production Data R36 (24h) – PGA Control Register 3 (PGA_CTRL3) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read 0 0 Write N/A N/A Default 0 0 Function PGA_SAFE_SW PGA Ramp ...
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WM8594 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS ADC Filter ± 0.05dB Passband Passband Ripple Stopband Stopband Attenuation Group Delay DAC Filter – 32kHz to 96kHz ± 0.1dB Passband Passband Ripple Stopband Stopband attenuation f > 0.546fs Group Delay DAC Filter ...
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Production Data DAC FILTER RESPONSES 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) Figure 54 DAC Digital Filter Frequency Response – 32kHz to 96kHz 0 -20 -40 -60 -80 -100 0 0.1 0.2 0.3 0.4 ...
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WM8594 DIGITAL DE-EMPHASIS CHARACTERISTICS - Frequency (kHz) Figure 58 De-Emphasis Frequency Response (32kHz) Figure 60 De-Emphasis Frequency Response (44.1KHz - Frequency (kHz) ...
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Production Data ADC FILTER RESPONSES Magnitude (dB 0.00 0.25 0.50 -20 -40 -60 -80 -100 -120 -140 Frequency Figure 64 ADC Digital Filter Frequency Response ADC HIGH PASS FILTER The WM8594 has a selectable digital ...
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WM8594 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Notes: 1. AGND and DGND should ideally share a continuous ground plane. Where this is not possible recommended that AGND and DGND are connected as close to the WM8594 as possible. 2. ...
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Production Data RECOMMENDED ANALOGUE LOW PASS FILTER Figure 67 Recommended Analogue Low Pass Filter (shown for VOUT1L/R) Note: See WAN0176 for AC coupling capacitor selection information. An external single pole RC filter is recommended (see Figure 67) if the device ...
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WM8594 RELEVANT APPLICATION NOTES The following application notes, available from www.wolfsonmicro.com, may provide additional guidance for the use of the WM8594. DEVICE PERFORMANCE: WAN0129 – Decoupling and Layout Methodology for Wolfson DACs, ADCs and CODECs WAN0144 – Using Wolfson Audio ...
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Production Data PACKAGE DIMENSIONS FT: 48 PIN TQFP ( 1.0 mm Dimensions Symbols (mm) MIN NOM A ----- ----- A 0.05 ----- 1 A 0.95 1.00 2 ...
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... WM8594 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...