wm8594seft-v Wolfson Microelectronics plc, wm8594seft-v Datasheet - Page 24

• Manufacturer Part Number: wm8594seft-v
• Description: 24-bit 192khz 2vrms Multi-channel Codec
• Manufacturer: Wolfson Microelectronics plc

WM8594
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DSP MODE B
In DSP Mode B, the MSB of channel 1 left data input is sampled on the first bit clock rising edge
following a left/right clock rising edge. Channel 1 right data then follows. The MSB of output data
changes on the same falling edge of BCLK as the low to high left/right clock transition and may be
sampled on the rising edge of bit clock. The right channel data is contiguous with the left channel
data.
Figure 17 DSP Mode B Timing
DIGITAL AUDIO INTERFACE CONTROL
The control of the audio interface formats is achieved by register write. Dynamically changing the
audio data format may cause erroneous operation and is not recommended.
Interface timing is such that the input data and left/right clock are sampled on the rising edge of the
interface bit clock. Output data changes on the falling edge of the interface bit clock. By setting the
appropriate bit clock and left/tight clock polarity bits, the WM8594 ADC and DACs can sample data
on the opposite clock edges.
The control of audio interface formats and clock polarities is summarised in Table 11.
DAC1_CTRL1
REGISTER
ADDRESS
02h
R2
BIT
1:0
3:2
4
DAC1_BCP
FMT[1:0]
WL[1:0]
LABEL
DAC1_
DAC1_
DEFAULT
10
10
0
DAC1 Audio Interface Format
00 = Right Justified
01 = Left Justified
10 = I
11 = DSP
DAC1 Audio Interface Word Length
00 = 16-bit
01 = 20-bit
10 = 24-bit
11 = 32-bit (not available in Right Justified
mode)
DAC1 BCLK Polarity
0 = DACBCLK not inverted - data latched on
rising edge of BCLK
1 = DACBCLK inverted - data latched on
falling edge of BCLK
2
S
DESCRIPTION
PD Rev 4.1 July 2008
Production Data
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