74AUP1G00GW,125 NXP Semiconductors, 74AUP1G00GW,125 Datasheet - Page 10

• Manufacturer Part Number: 74AUP1G00GW,125
• Description: IC 2-IN NAND GATE LP 5-TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74AUPr

Specifications of 74AUP1G00GW,125

• Number Of Circuits: 1
• Package / Case: SC-70-5, SC-88A, SOT-323-5, SOT-353, 5-TSSOP
• Logic Type: NAND Gate
• Number Of Inputs: 2
• Current - Output High, Low: 4mA, 4mA
• Voltage - Supply: 0.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Product: NAND
• Logic Family: 74AUP
• High Level Output Current: - 4 mA
• Low Level Output Current: 4 mA
• Propagation Delay Time: 17.5 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0.8 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Output Current: 20 mA
• Output Voltage: 3.6 V
• Power Dissipation: 250 mW
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2546-2; 935278998125

NXP Semiconductors
Table 9.
Voltages are referenced to GND (ground = 0 V); for test circuit see
[1]
12. Waveforms
Table 10.
74AUP1G00
Product data sheet
Symbol
C
t
C
t
Supply voltage
V
0.8 V to 3.6 V
pd
pd
Fig 7. The data input (A or B) to output (Y) propagation delays
CC
L
L
= 15 pF
= 30 pF
t
pd
is the same as t
Measurement points are given in
Logic levels: V
Dynamic characteristics
Measurement points
Parameter
propagation delay
propagation delay
PLH
OL
and t
and V
PHL
Output
V
0.5 × V
OH
M
.
are typical output voltage drop that occur with the output load.
Conditions
A, B to Y; see
A, B to Y; see
V
V
V
V
V
V
V
V
V
V
A, B input
CC
Y output
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
…continued
Table
= 1.1 V to 1.3 V
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3.0 V to 3.6 V
= 1.1 V to 1.3 V
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3.0 V to 3.6 V
All information provided in this document is subject to legal disclaimers.
GND
10.
V
V
OH
OL
V
I
Figure 7
Figure 7
Rev. 3 — 7 October 2010
Input
V
0.5 × V
M
V
M
V
CC
M
t
PHL
[1]
[1]
Figure 8
−40 °C to +85 °C
Min
3.1
4.1
2.9
2.5
2.0
1.5
1.4
2.3
2.1
2.1
V
V
I
CC
mna612
Max
16.5
10.5
22.6
14.0
t
11.1
8.3
6.4
5.7
8.5
7.6
PLH
Low-power 2-input NAND gate
−40 °C to +125 °C
Min
74AUP1G00
3.1
2.5
2.0
1.5
1.4
4.1
2.9
2.3
2.1
2.1
t
≤ 3.0 ns
r
= t
© NXP B.V. 2010. All rights reserved.
f
Max
18.2
24.9
15.4
12.3
11.6
9.2
7.1
6.3
9.4
8.4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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