74LVC1G10GW,125 NXP Semiconductors, 74LVC1G10GW,125 Datasheet - Page 6

• Manufacturer Part Number: 74LVC1G10GW,125
• Description: IC SINGLE 3IN NAND GATE UMT6
• Manufacturer: NXP Semiconductors
• Series: 74LVCr

Specifications of 74LVC1G10GW,125

• Number Of Circuits: 1
• Package / Case: SC-70-6, SC-88, SOT-363
• Logic Type: NAND Gate
• Number Of Inputs: 3
• Current - Output High, Low: 32mA, 32mA
• Voltage - Supply: 1.65 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: LVC
• High Level Output Current: - 32 mA
• Low Level Output Current: 32 mA
• Propagation Delay Time: 3 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.65 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74LVC1G10GW-G; 74LVC1G10GW-G; 935284948125

NXP Semiconductors
11. Dynamic characteristics
Table 8.
Voltages are referenced to GND (ground = 0 V). For test circuit see
[1]
[2]
[3]
12. Waveforms
74LVC1G10
Product data sheet
Symbol Parameter
t
C
pd
Fig 7.
PD
Typical values are measured at T
t
C
P
f
f
C
V
N = number of inputs switching;
Σ(C
pd
i
o
D
CC
PD
= input frequency in MHz;
L
= output frequency in MHz;
is the same as t
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in V;
× V
propagation delay A, B and C to Y; see
power dissipation
capacitance
Measurement points are given in
V
The input (A, B, C) to output (Y) propagation delays
PD
OL
Dynamic characteristics
CC
× V
2
and V
× f
CC
o
2
) = sum of the outputs.
OH
× f
PLH
i
are typical output voltage levels that occur with the output load.
× N + Σ(C
and t
PHL
Conditions
V
L
I
.
V
V
V
V
V
= GND to V
× V
amb
CC
CC
CC
CC
CC
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 4.5 V to 5.5 V
= 25 °C and V
2
× f
Table
Y output
A, B, C,
o
All information provided in this document is subject to legal disclaimers.
) where:
input
CC
9.
; V
GND
V
V
OH
OL
V
CC
Rev. 2 — 21 October 2010
CC
I
Figure 7
= 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
= 3.3 V
V
M
D
t
PLH
in μW).
V
[2]
[3]
M
Figure
Min
1.5
1.0
1.0
1.0
1.0
-
−40 °C to +85 °C
8.
t
PHL
001aag692
Typ
4.7
3.0
3.0
2.6
1.9
12
[1]
Max
18.0
6.5
6.0
5.0
3.6
-
Single 3-input NAND gate
74LVC1G10
−40 °C to +125 °C Unit
Min
1.5
1.0
1.0
1.0
1.0
-
© NXP B.V. 2010. All rights reserved.
Max
21.5
7.8
7.5
6.2
4.4
-
ns
ns
ns
ns
ns
pF
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