gal26cv12 Lattice Semiconductor Corp., gal26cv12 Datasheet - Page 12

• Manufacturer Part Number: gal26cv12
• Description: High Performance E2 Cmos Pld Generic Array Logic? Gal26cv12 Gal
• Manufacturer: Lattice Semiconductor Corp.

An electronic signature is provided in every GAL26CV12 device.
It contains 64 bits of reprogrammable memory that can contain
user-defined data. Some uses include user ID codes, revision
numbers, or inventory control. The signature data is always avail-
able to the user independent of the state of the security cell.
A security cell is provided in every GAL26CV12 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de-
vice, so the original configuration can never be examined once this
cell is programmed. The Electronic Signature is always available
to the user, regardless of the state of this control cell.
GAL26CV12 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias minimizes the
potential for latch-up caused by negative input undershoots. Ad-
ditionally, outputs are designed with n-channel pull-ups instead of
the traditional p-channel pull-ups in order to eliminate latch-up due
to output overshoots.
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the the GAL Development Tools section). Complete
programming of the device takes only a few seconds. Erasing of
the device is transparent to the user, and is done automatically as
part of the programming cycle.
Electronic Signature
Security Cell
Latch-Up Protection
Device Programming
12
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in normal machine operation. This is because certain events may
occur during system operation that throw the logic into an illegal
state (power-up, line voltage glitches, brown-outs, etc.). To test a
design for proper treatment of these conditions, a way must be
provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
The GAL26CV12 device includes circuitry that allows each regis-
tered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If nec-
essary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.
GAL26CV12 devices are designed with TTL level compatible in-
put buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
logic.
The input and I/O pins also have built-in active pull-ups. As a result,
floating inputs will float to a TTL high (logic 1). However, Lattice
Semiconductor recommends that all unused inputs and tri-stated
I/O pins be connected to an adjacent active input, Vcc, or ground.
Doing so will tend to improve noise immunity and reduce Icc for the
device.
Output Register Preload
Input Buffers
- 4 0
- 2 0
- 6 0
0
Specifications GAL26CV12
0
1 . 0
Typical Input Current
In p u t V o lt ag e ( V o lt s)
2 . 0
3 . 0
4 . 0
5 . 0