m52s128324a Elite Semiconductor Memory Technology Inc., m52s128324a Datasheet - Page 14

• Manufacturer Part Number: m52s128324a
• Description: 1m X 32 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
DEVICE OPERATIONS (Continued)
AUTO REFRESH
The storage cells of SDRAM need to be refreshed every 64ms
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the
rows. An auto refresh command is issued by asserting low on
refresh command can only be asserted with all banks being in
idle state and the device is not in power down mode (CKE is
high in the previous cycle). The time required to complete the
auto refresh operation is specified by t
number of clock cycles required can be calculated by driving
t
higher integer. The auto refresh command must be followed by
NOP’s until the auto refresh operation is completed. The auto
refresh is the preferred refresh mode when the SDRAM is
being used for normal data transactions. The auto refresh
cycle can be performed once in 15.6us or the burst of 4096
auto refresh cycles in 40ms.
Elite Semiconductor Memory Technology Inc.
CS , RAS and CAS with high on CKE and WE . The auto
RC
with clock cycle time and them rounding up to the next
RC (min)
. The minimum
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and
all the input buffers except CKE. The refresh addressing
and timing is internally generated to reduce power
consumption.
The self refresh mode is entered from all banks idle state
by asserting low on CS , RAS , CAS and CKE with
high on WE . Once the self refresh mode is entered, only
CKE state being low matters, all the other inputs including
clock are ignored to remain in the refresh.
SELF REFRESH
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed by
NOP’s for a minimum time of t
reaches idle state to begin normal operation. 4K cycles of
burst auto refresh is required immediately before self
refresh entry and immediately after self refresh exit.
Publication Date: Mar. 2009
Revision: 1.4
M52S128324A
RC
before the SDRAM
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