m52s128324a Elite Semiconductor Memory Technology Inc., m52s128324a Datasheet - Page 7

• Manufacturer Part Number: m52s128324a
• Description: 1m X 32 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
AC CHARACTERISTICS (AC operating condition unless otherwise noted)
Note :
Elite Semiconductor Memory Technology Inc.
Col. address to col. address delay
Number of valid
Output data
CLK cycle time
CLK to valid
output delay
Output data
hold time
CLK high pulsh width
CLK low pulsh width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
rounding off to the next higher integer.
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
Parameter
Parameter
CAS latency = 3
CAS latency = 2
CAS latency = 1
CAS latency = 3
CAS latency = 2
CAS latency = 1
CAS latency = 3
CAS latency = 2
CAS latency = 1
CAS latency = 3
CAS latency = 2
CAS latency = 1
CAS latency = 3
CAS latency = 2
CAS latency = 1
t
CCD(min)
Symbol
Symbol
t
t
t
t
t
t
t
t
t
SAC
SHZ
SLZ
OH
CC
CH
SS
SH
CL
Min
8.6
2.5
2.5
20
7
2
2
2
2
1
1
-
-
-
-
-
-
-7
-7
Version
1000
Max
1
2
1
0
18
18
6
7
6
7
-
-
-
-
-
-
-
-
-10
2.5
1.5
Min
10
12
20
2
2
2
3
3
1
-
-
-
-
-
-
-10
1000
Max
18
18
9
8
9
8
-
-
-
-
-
-
-
-
Unit
CLK
ea
Publication Date: Mar. 2009
Revision: 1.4
M52S128324A
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
3
4
Note
1,2
1
2
3
3
3
3
2
-
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