m52s128324a Elite Semiconductor Memory Technology Inc., m52s128324a Datasheet - Page 21

• Manufacturer Part Number: m52s128324a
• Description: 1m X 32 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
5. Write Interrupted by Precharge & DQM
*Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
Elite Semiconductor Memory Technology Inc.
D Q M
C M D
C L K
D Q
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt
1 ) N o r m a l W r i t e ( B L = 4 )
( b ) C L = 3 , B L = 4
but only another bank precharge of four banks operation.
i i i ) C M D
i v ) C M D
i i ) C M D
v ) C M D
i ) C M D
W R
D 0
D Q M
D Q M
D Q M
D Q M
C L K
D Q M
D Q
D Q
D Q
D Q
D Q
D 1
D 2
t
RDL(min)
D 3
M a s k e d b y D Q M
* N o t e 2
R D
R D
R D
R D
R D
P R E
* N o t e 3
W R
D 0
W R
D 1
D 0
H i - Z
W R
Q0
D 2
D 1
D 0
* N o t e 1
H i - Z
W R
D 3
D 2
D 0
D 1
W R
D 2
D 1
D 0
D 3
D 3
D 2
D 1
D 3
D 2
D 3
Publication Date: Mar. 2009
Revision: 1.4
M52S128324A
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