74HC240N,652 NXP Semiconductors, 74HC240N,652 Datasheet
74HC240N,652
Specifications of 74HC240N,652
933670520652
Related parts for 74HC240N,652
74HC240N,652 Summary of contents
Page 1
Octal buffer/line driver; 3-state; inverting Rev. 03 — 2 August 2007 1. General description The 74HC240; 74HCT240 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC240; 74HCT240 is a dual ...
Page 2
... NXP Semiconductors Table 1. Ordering information Type number Package Temperature range Name 74HCT240D +125 C 74HCT240DB +125 C 74HCT240PW +125 C 74HCT240BQ +125 C 4. Functional diagram 2 1A0 1Y0 17 2A0 2Y0 4 1A1 1Y1 15 2A1 2Y1 6 1A2 1Y2 13 2A2 2Y2 8 1Y3 1A3 11 2A3 2Y3 1OE 1 19 2OE mgu779 Fig 1 ...
Page 3
... NXP Semiconductors 5. Pinning information 5.1 Pinning 74HC240 74HCT240 1 1OE 2 1A0 2Y0 3 1A1 4 5 2Y1 1A2 6 2Y2 7 1A3 8 9 2Y3 GND 10 Fig 4. Pin configuration DIP20, SO20, (T)SSOP20 5.2 Pin description Table 2. Pin description Symbol Pin 1OE 1 1A0 2 2Y0 3 1A1 4 2Y1 5 1A2 ...
Page 4
... NXP Semiconductors Table 2. Pin description …continued Symbol Pin 2A0 17 1Y0 18 2OE Functional description [1] Table 3. Function table Input nOE [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...
Page 5
... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter 74HC240 V supply voltage CC V input voltage I V output voltage input transition rise and fall rate V T ambient temperature amb 74HCT240 V supply voltage CC V input voltage I V output voltage input transition rise and fall rate V ...
Page 6
... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V LOW-level output voltage 6.0 mA 7.8 mA input leakage current OFF-state per input pin output current other inputs 6 supply current 6 input I capacitance 74HCT240 V HIGH-level 5.5 V ...
Page 7
... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for load circuit see Figure Symbol Parameter Conditions 74HC240 t propagation delay nAn to nYn; pd see enable time nOE to nYn; see disable time nOE to nYn or see dis transition time see power dissipation per transceiver; ...
Page 8
... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V; for load circuit see Figure Symbol Parameter Conditions 74HCT240 t propagation delay nAn to nYn; pd see enable time nOE to nYn Figure 7 t disable time nOE to nYn; V dis Figure 7 t transition time power dissipation per transceiver; PD capacitance ...
Page 9
... NXP Semiconductors nOE input nYn output LOW-to-OFF OFF-to-LOW nYn output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical voltage output drop that occur with the output load Fig 7. 3-state enable and disable times Table 8. Measurement points Type Input V M 74HC240 ...
Page 10
... NXP Semiconductors PULSE GENERATOR Test data is given in Table 9. Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 8. Load circuitry for measuring switching times Table 9. Test data Type ...
Page 11
... NXP Semiconductors 12. Package outline DIP20: plastic dual in-line package; 20 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
Page 12
... NXP Semiconductors SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
Page 13
... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 11. Package outline SOT339-1 (SSOP20) ...
Page 14
... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
Page 15
... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
Page 16
... Data sheet status Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added type number 74HC240BQ and 74HCT240BQ (DHVQFN20 package) Product specifi ...
Page 17
... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
Page 18
... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14 Revision history ...