92hd98 Integrated Device Technology, 92hd98 Datasheet - Page 14

• Manufacturer Part Number: 92hd98
• Description: Datasheet
• Manufacturer: Integrated Device Technology

92HD98
SINGLE CHIP PC AUDIO SYSTEM, CODEC+MONO SPEAKER AMPLIFIER+CAPLESS HP+LDO
IDT CONFIDENTIAL
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
2.1.2.
2.1.3.
2.1.4.
Vref_Out
Ports C, & A support Vref_Out pins for biasing electret cartridge microphones. Settings of 80%
AVDD, 50% AVDD, GND, and Hi-Z are supported. Attempting to program a pin widget control with a
reserved or unsupported value will cause the associated Vref_Out pin to assume a Hi-Z state and
the pin widget control Vref_En field will return a value of ‘000’ (Hi-Z) when read.
Jack Detect
Plugs inserted to a jack on Ports A, B, C & SPDIFOUT0 are detected using SENSE_A. Plugs
inserted to a jack on Ports E,F, DMIC0, & SPDIFOUT1 are detected using SENSE_B. Per
HDA015-B, the detection circuit operates when the CODEC is in D0 - D3 and can also operate if
both the CODEC and Controller are in D3 (no bus clock.) Jack detection requires that all supplies
(analog and digital) are active and stable. When AVDD is not present, the value reported in the pin
widget is invalid.
When the HD Audio bus is in a low power state (reset asserted and clock stopped) the CODEC will
generate a Power State Change Request when a change in port connectivity is sensed and then
generate an unsolicited response after the HD Audio link has been brought out of a low power state
and the device has been enumerated. Per HDA015-B, this will take less than 10mS.
The following table summarizes the proper resistor tolerances for different analog supply voltages..
See reference design for more information on Jack Detect implementation.
SPDIF Output
Both SPDIF Outputs can operate at 44.1kHz, 48kHz, 88.2kHz, 96kHz and 192KHz as defined in the
Intel High Definition Audio Specification with resolutions up to 24 bits. This insures compatibility with
all consumer audio gear and allows for convenient integration into home theater systems and media
center PCs.
The two SPDIF output converters can not be aligned in phase with the DACs. Even when attached
to the same stream, the two SPDIF output converters may be misaligned with respect to their frame
boundaries.
Voltage (+/- 5%)
AVdd Nominal
Resistor
4.75V
39.2K
20.0K
10.0K
5.11K
2.49K
Table 3. 48pin Jack Detect
Resistor Tolerance
Pull-up to AVDD
PORT A (HP0)
PORT B (HP1)
SPDIFOUT0
SENSE_A
PORT C
Pull-Up
1%
14
Resistor Tolerance
Pull-up to AVDD
SENSE_A/B
SPDIFOUT1
SENSE_B
(DMIC1)
PORT F
DMIC0
1%
V 0.91 10/10
92HD98