92hd98 Integrated Device Technology, 92hd98 Datasheet - Page 265

• Manufacturer Part Number: 92hd98
• Description: Datasheet
• Manufacturer: Integrated Device Technology

92HD98
SINGLE CHIP PC AUDIO SYSTEM, CODEC+MONO SPEAKER AMPLIFIER+CAPLESS HP+LDO
IDT CONFIDENTIAL
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
The EQRAM is programmed indirectly through the Control Bus in the following manner:
1) Write the 48-bit write data to the EQRAM_WRITE register
2) Write the target address to the EQ_ADDRESS register
3) Set bit 7 of the EQRAM_CTRL register
The write will occur when the EQRAM is not being accessed by the DSP audio processing routines. When complete
the hardware will automatically clear this bit.
Reading back from the EQRAM is done in the following manner:
1) Write target address to EQ_ADDR register
2) Set bit 6 of the EQRAM_CTRL register
When the hardware completes the read it will automatically clear this bit.
3) When bit 6 of the EQRAM_CTRL register has been cleared, read the 48bit data from the EQRAM_READ register.
Address
EQRAM
0x1C
0x1D
0x2C
0x2D
0x1A
0x1B
0x1E
0x1F
0x2A
0x2B
0x2E
0x2F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x30
0x31
0x32
0x33
Bits
Channel Left Coefficients (24bit)
EQ_COEF_F0_B0
EQ_COEF_F0_B1
EQ_COEF_F0_B2
EQ_COEF_F0_A1
EQ_COEF_F0_A2
EQ_COEF_F1_B0
EQ_COEF_F1_B1
EQ_COEF_F1_B2
EQ_COEF_F1_A1
EQ_COEF_F1_A2
EQ_COEF_F2_B0
EQ_COEF_F2_B1
EQ_COEF_F2_B2
EQ_COEF_F2_A1
EQ_COEF_F2_A2
EQ_COEF_F3_B0
EQ_COEF_F3_B1
EQ_COEF_F3_B2
EQ_COEF_F3_A1
EQ_COEF_F3_A2
EQ_COEF_F4_B0
EQ_COEF_F4_B1
EQ_COEF_F4_B2
EQ_COEF_F4_A1
EQ_COEF_F4_A2
EQ_PRESCALE
[47:24]
based on 48Khz sample rate
265
Channel Right Coefficients (24bit)
EQ_COEF_F0_B0
EQ_COEF_F0_B1
EQ_COEF_F0_B2
EQ_COEF_F0_A1
EQ_COEF_F0_A2
EQ_COEF_F1_B0
EQ_COEF_F1_B1
EQ_COEF_F1_B2
EQ_COEF_F1_A1
EQ_COEF_F1_A2
EQ_COEF_F2_B0
EQ_COEF_F2_B1
EQ_COEF_F2_B2
EQ_COEF_F2_A1
EQ_COEF_F2_A2
EQ_COEF_F3_B0
EQ_COEF_F3_B1
EQ_COEF_F3_B2
EQ_COEF_F3_A1
EQ_COEF_F3_A2
EQ_COEF_F4_B0
EQ_COEF_F4_B1
EQ_COEF_F4_B2
EQ_COEF_F4_A1
EQ_COEF_F4_A2
EQ_PRESCALE
[23:00]
V 0.91 10/10
92HD98