mt89l85apr1 Zarlink Semiconductor, mt89l85apr1 Datasheet - Page 5

• Manufacturer Part Number: mt89l85apr1
• Description: 256 X 256 Channels 8 Tdm Streams At 2.048 Mbps 3.3 V Non-blocking Enhance Digital Switch Edx With Constant Delay Mode
• Manufacturer: Zarlink Semiconductor

interface. Upon determining the correct interface connected to the serial port, the internal timing unit establishes the
appropriate serial data bit transmit and sampling edges. In ST-BUS mode, every second falling edge of the
4.096 MHz clock marks a bit boundary and the input data is clocked in by the rising edge, three quarters of the way
into the bit cell. In GCI mode, every second rising edge of the 4.096 MHz clock marks the bit boundary while data
sampling is performed during the falling edge, at three quarters of the bit boundaries.
Delay through the MT89L85
The transfer of information from the input serial streams to the output serial streams results in a delay through the
MT89L85 device. The delay through the device varies according to the mode selected in the V/C bit of the connect
memory high.
Variable Delay mode
The delay in this mode is dependent only on the combination of source and destination channels and it is not
dependent on the input and output streams. The minimum delay achievable in the MT89L85 device is 3 time slots.
In the MT89L85 device, the information that is to be output in the same channel position as the information is input
(position n), relative to frame pulse, will be output in the following frame (channel n, frame n+1). The same occurs if
the input channel has to be output in the two channels succeeding (n+1 and n+2) the channel position as the
information is input.
The information switched to the third timeslot after the input has entered the device (for instance, input channel 0 to
output channel 3 or input channel 30 to output channel 1), is always output three channels later.
Any switching configuration that provides three or more timeslots between input and output channels, will have a
throughput delay equal to the difference between the output and input channels; i.e., the throughput delay will be
less than one frame. Table 1 shows the possible delays for the MT89L85 device in Variable Delay mode:
Constant Delay Mode
In this mode frame integrity is maintained in all switching configurations by making use of a multiple Data-Memory
buffer technique where input channels written in any of the buffers during frame N will be read out during frame
N+2. In the MT89L85, the minimum throughput delay achieve-able in Constant Delay mode will be 32 time slots; for
example, when input time slot 32 (channel 31) is switched to output time slot 1 (channel 0). Likewise, the maximum
delay is achieved when the first time slot in a frame (channel 0) is switched to the last time slot in the frame
(channel 31), resulting in 94 time slots of delay.
Table 1 - Channel Delays for the Variable Delay Mode
Channel
Input
n
n
n
m=n, n+1 or
Zarlink Semiconductor Inc.
Channel
Output
m>n+2
m<n
MT89L85
n+2
5
Throughput Delay
32-(n-m) time slots
m-n + 32 timeslots
m-n time slots
Data Sheet