mt89l85apr1 Zarlink Semiconductor, mt89l85apr1 Datasheet - Page 8

• Manufacturer Part Number: mt89l85apr1
• Description: 256 X 256 Channels 8 Tdm Streams At 2.048 Mbps 3.3 V Non-blocking Enhance Digital Switch Edx With Constant Delay Mode
• Manufacturer: Zarlink Semiconductor

x = Don’t care
4-3
2-0
Bit
7
6
MS1-MS0
STA2-0
Name
ME
SM
Split Memory. When 1, all subsequent reads are from the Data Memory and writes are to the
Connection Memory Low, except when the Control Register is accessed again. The Memory Select
bits need to be set to specify the memory for the operations. When 0, the Memory Select bits
specify the memory for subsequent operations. In either case, the Stream Address Bits select the
subsection of the memory which is made available.
Message Enable. When 1, the contents of the Connection Memory Low are output on the Serial
Output streams except when in High Impedance. When 0, the Connection Memory bits for each
channel determine what is output.
Memory Select Bits. The memory select bits operate as follows:
Stream Address Bits 2-0. The number expressed in binary notation on these bits refers to the input
or output ST-BUS stream which corresponds to the subsection of memory made accessible for
subsequent operations.
SM
7
1-0 - Connection Memory Low
1-1 - Connection Memory High
0-0 - Not to be used
0-1 - Data Memory (read only from the CPU)
ME
6
Figure 4 - Control Register Bits
X
5
Zarlink Semiconductor Inc.
MT89L85
MS1
4
8
MS0
3
Description
STA2
2
STA1
1
STA0
0
Data Sheet