mt89l85apr1 Zarlink Semiconductor, mt89l85apr1 Datasheet - Page 6

• Manufacturer Part Number: mt89l85apr1
• Description: 256 X 256 Channels 8 Tdm Streams At 2.048 Mbps 3.3 V Non-blocking Enhance Digital Switch Edx With Constant Delay Mode
• Manufacturer: Zarlink Semiconductor

To summarize, any input time slot from input frame N will be always switched to the destination time slot on output
frame N+2. In Constant Delay mode, the device throughput delay is calculated according to the following formula:
Where:
Microprocessor Port
The MT89L85 microprocessor port has pin compatibility with Zarlink MT8985 Digital Switch devices providing a
non-multiplexed bus architecture. The parallel port consists of an 8 bit parallel data bus (D0-D7), six address input
lines (A0-A5) and four control lines (CS, DS, R/W and DTA). This parallel microport allows the access to the Control
registers, Connection Memory High, Connection Memory Low and the Data Memory. All locations are read/written
except for the data memory which can be read only.
Accesses from the microport to the connection memory and the data memory are multiplexed with accesses from
the input and output TDM ports. This can cause variable Data Acknowledge delays (DTA).
Software Control
The address lines on the microprocessor interface give access to the MT89L85 internal registers and memories. If
the A5,A1,A0 address line inputs are LOW, then the MT89L85 Internal Control Register is addressed (see Figure
3). If A5 input line is HIGH, then the remaining address input lines are used to select Memory subsections of 32
locations corresponding to the number of channels per input or output stream. As explained in the Control register
description, the address input lines and the Stream Address bits (STA) of the Control register give the user the
capability of selecting all positions of the MT89L85 Data and Connect memories.
The data in the Control register consists of Split memory and Message mode bits, Memory select and Stream
Address bits (see Figure 4). The memory select bits allow the Connect Memory HIGH or LOW or the Data Memory
to be chosen, and the Stream Address bits define an internal memory subsections corresponding to input or output
ST-BUS streams. Bit 7 (Split Memory) of the Control register allows split memory operation whereby reads are
from the Data memory and writes are to the Connect Memory LOW.
The Message Enable bit (bit 6) places every output channel on every output stream in message mode; i.e., the
contents of the Connect Memory LOW (CML) are output on the ST-BUS output streams once every frame unless
DELAY = [32 + (32 - IN) + (OUT - 1)];
(expressed in number of time slots)
IN is the number of the input time slot
OUT is the number of the output time slot
(from 1 to 32).
(from 1 to 32).
Note: "x" Don’t care.
A5
0
1
1
1
1
1
1
1
1
A4
0
0
0
1
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•
•
•
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A3
Figure 3 - Address Memory Map
0
0
0
1
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Zarlink Semiconductor Inc.
A2
0
0
0
1
•
•
•
•
•
MT89L85
A1
0
0
0
1
•
•
•
•
•
6
A0
0
0
1
1
•
•
•
•
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Control Register
LOCATION
Channel 31
Channel 0
Channel 1
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Data Sheet