htrc11001t/03ee NXP Semiconductors, htrc11001t/03ee Datasheet - Page 5

• Manufacturer Part Number: htrc11001t/03ee
• Description: Hitag Reader Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
9. Functional description
037031
Product data sheet
PUBLIC
9.1 Power supply
9.2 Antenna driver, data input
9.3 Diagnosis
9.4 Oscillator/programmable divider/clock
9.5 Adaptive sampling time demodulator
The HTRC110 works with an external 5 V± 10 % power supply at VDD. The maximum
DC-current is 10 mA+Î
connection should be by-passed to ground with a 100 nF capacitor close to the IC.
The drivers deliver a square shaped voltage to the series resonant antenna circuit. Due to
the full bridge configuration of the drivers this voltage U
(peak-peak) corresponding to Û
shaped. It´s amplitude is approximately:
In order to detect an antenna short or open condition the antenna tap voltage is
monitored. An antenna fail condition is reported in the status bit ANTFAIL (see
if the antenna tap voltage does not go more negative than the diagnosis level DLEV (see
Table
The crystal oscillator at XTAL1/2 works with either crystal or ceramic resonators. It
delivers the input clock frequency of 4, 8, 12 or 16 MHz. The oscillator frequency is
divided by a programmable divider to obtain the carrier frequency of 125 kHz (see
Table
IC via XTAL1. For example, this signal can be derived from the microcontroller clock.
The demodulator senses the absorption modulation applied by a transponder when
inserted into the field. The signal is picked up at the antenna tap point between L
It is divided by R
to QGND at the RX-pin (see
low pass filter.
The antenna current and therefore the tap voltage is modulated by the transponder in
amplitude and/or phase. This signal is fed into a synchronous demodulator recovering the
baseband signal. The amplification and the bandpass filter edge frequencies of the
demodulator can be adapted to different transponders via settings in the configuration
pages.
18). This condition is checked for every coil driver cycle.
12). Alternatively, an external clock signal (CMOS compatible) may be fed into the
All information provided in this document is subject to legal disclaimers.
v
and the internal resistor R
Rev. 3.1 — 9 February 2010
ant
*2/ π = 137 mA. For optimum performance, the power supply
Figure
037031
drv
= 5 V. The current flowing through the antenna is sine
3). Internally the signal is filtered with a second order
dem_in
to a level below 8 V (peak) with respect
drvpp
is approximately 10 V
HTRC110
HITAG reader chip
© NXP B.V. 2010. All rights reserved.
Table
a
and C
5 of 22
16),
a
.