89hpes24t6g2 Integrated Device Technology, 89hpes24t6g2 Datasheet - Page 13

• Manufacturer Part Number: 89hpes24t6g2
• Description: 24-lane, 6-port Gen2 Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

IDT 89HPES24T6G2 Data Sheet
T
DATA
T
T
T
T
T
PCIe Receive
UI
T
T
MAX JITTER
T
T
T
T
T
TX-IDLE-TO-DIFF-
TX-SKEW
MIN-PULSED
MEAS-HPF
TX-HF-DJ-DD
RF-MISMATCH
RX-EYE (with jitter)
RX-EYE-MEDIUM TO
RX-SKEW
RX-HF-RMS
RX-HF-DJ-DD
RX-LF-RMS
RX-MIN-PULSE
1.
Parameter
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0
Maximum time to transition from valid idle to diff data
Transmitter data skew between any 2 lanes
Minimum Instantaneous Lone Pulse Width
Transmit Jitter Measurement Filter
Transmitter Deterministic Jitter > 1.5MHz Bandwidth
Rise/Fall Time Differential Mismatch
Unit Interval
Minimum Receiver Eye Width (jitter tolerance)
Max time between jitter median & max deviation
Lane to lane input skew
1.5 — 100 MHz RMS jitter
Maximum tolerable DJ by the receiver
10 KHz to 1.5 MHz RMS jitter
Minimum receiver instantaneous eye width
GPIO
GPIO[10:0]
1.
they are asynchronous. Note that GPIO{6:3} pins are not available in the 19mm package.
2.
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
The values for this symbol were determined by calculation, not by testing.
Signal
1
Description
Table 10 PCIe AC Timing Characteristics (Part 2 of 2)
Symbol
Tpw
Table 11 GPIO AC Timing Characteristics
2
Referenc
e Edge
None
13 of 51
Min
399.88
0.4
Min Max Unit
50
1
HPF: 1.5MHz
Gen 1
Typ
400
NA
NA
NA
NA
NA
NA
NA
—
1
ns
Max
400.12
1.3
0.3
20
8
1
Reference
Diagram
Timing
Min
199.94
0.9
0.4
0.6
1
HPF: 1.0MHz
Gen 2
Typ
1
Max
200.06
0.15
1.3
0.1
4.2
8.8
4.2
8
8
1
May 7, 2008
Units
MHz
ns
ns
ps
ns
ps
ps
ps
UI
UI
UI
UI
UI
UI