89hpes24t6g2 Integrated Device Technology, 89hpes24t6g2 Datasheet - Page 2

• Manufacturer Part Number: 89hpes24t6g2
• Description: 24-lane, 6-port Gen2 Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

Product Description
provides the most efficient I/O connectivity solution for applications
requiring high throughput, low latency, and simple board layout with a
minimum number of board layers. It provides connectivity for up to 6
ports across 24 integrated serial lanes. Each lane provides 5 Gbps of
bandwidth in both directions and is fully compliant with PCI Express
Base Specification, Revision 2.0, including operation in 5 Gbps, 2.5
Gbps, and mixed 5 Gbps / 2.5Gbps modes.
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
IDT 89HPES24T6G2 Data Sheet
Utilizing standard PCI Express interconnect, the PES24T6G2
The PES24T6G2 is based on a flexible and efficient layered architec-
– Hot-swap capable I/O
– External Serial EEPROM contents are checksum protected
– Supports PCI Express Device Serial Number Capability
– Capability to monitor link reliability and autonomously change
– Utilizes advanced low-power design techniques to achieve low
– Support PCI Power Management Interface specification (PCI-
– Support for PCI Express Active State Power Management
– Supports PCI Express Power Budgeting Capability
– Configurable SerDes power consumption
– Unused SerDes are disabled
– Per port link up and activity status outputs available on I/O
– Built in SerDes 8-bit and 10-bit pseudo-random bit stream
– Numerous SerDes test modes, including a PRBS Master
– Ability to read and write any internal register via SMBus and
– Per port statistics and performance counters, as well as propri-
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Power Management
Testability and Debug Features
Eleven General Purpose Input/Output Pins
Option A Package: 19mm x 19mm 324-ball Flip Chip BGA
with 1mm ball spacing
Option B Package: 27mm x 27mm 676-ball Flip Chip BGA
with 1mm ball spacing
• Supports device power management states: D0, D3
• Supports link power management states: L0, L0s, L1, L2/L3
• Supports optional PCI-Express SerDes Transmit Low-Swing
• Supports numerous SerDes Transmit Voltage Margin
link speed to prevent link instability
typical power consumption
PM 1.1)
(ASPM) link state
expander outputs
(PRBS) generators
Loopback mode for in-system link testing
JTAG interfaces, including SerDes internal controls
etary link status registers
D3
Ready and L3
Voltage Mode
settings
cold
*Notice: The information in this document is subject to change without notice
hot
and
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Revision 2.0. The PES24T6G2 can operate either as a store and
forward or cut-through switch and is designed to switch memory and I/O
transactions. It supports eight Traffic Classes (TCs) and one Virtual
Channel (VC) with sophisticated resource management to enable effi-
cient switching and I/O connectivity for servers, storage, and embedded
processors with limited connectivity.
SMBus Interface
face provides full access to the configuration registers in the
PES24T6G2, allowing every configuration register in the device to be
read or written by an external agent. The master interface allows the
default configuration register values of the PES24T6G2 to be over-
ridden following a reset with values programmed in an external serial
EEPROM. The master interface is also used by an external Hot-Plug I/O
expander.
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the
SMBus address to which the device responds to be configured. In the
master interface, these address pins allow the SMBus address of the
serial configuration EEPROM from which data is loaded to be config-
ured. The SMBus address is set up on negation of PERSTN by
sampling the corresponding address pins. When the pins are sampled,
the resulting address is assigned as shown in Table 1.
The PES24T6G2 contains two SMBus interfaces. The slave inter-
Six pins make up each of the two SMBus interfaces. These pins
Note: MSMBADDR and SSMBADDR address pins are not
available in the 19mm package. The MSMBADDR address is
hardwired to 0x50, and the SSMBADDR address is hardwired
to 0x77.
PCI Express
x4
Slots
Figure 2 I/O Expansion Application
Processor
PES24T6G2
x4
x8
10GbE
I/O
x4
Bridge
North
Processor
10GbE
I/O
x4
SATA
I/O
Memory
Memory
Memory
Memory
SATA
May 7, 2008
I/O