89hpes24t6g2 Integrated Device Technology, 89hpes24t6g2 Datasheet - Page 7

• Manufacturer Part Number: 89hpes24t6g2
• Description: 24-lane, 6-port Gen2 Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

IDT 89HPES24T6G2 Data Sheet
1.
2.
JTAG_TRST_N
SWMODE[2:0]
MSMBSMODE is not available in the 19mm package, resulting in the master SMBus operating only at 400 KHz.
RSTHALT is not available in the 19mm package.
JTAG_TCK
JTAG_TDO
JTAG_TMS
RSTHALT
JTAG_TDI
Signal
Signal
2
Type
Type
O
I
I
I
I
I
I
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, PES24T6G2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
Switch Mode. These configuration pins determine the PES24T6G2 switch
operating mode.
0x0 -Normal switch mode
0x1 -Normal switch mode with Serial EEPROM initialization
0x2 - through 0x7 Reserved
These pins should be static and not change following the negation of
PERSTN.
JTAG Clock. This is an input test clock used to clock the shifting of data into
or out of the boundary scan logic or JTAG Controller. JTAG_TCK is indepen-
dent of the system clock with a nominal 50% duty cycle.
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is rec-
ommended to meet the JTAG specification in cases where the tester can
access this signal. However, for systems running in functional mode, one of
the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 5 System Pins (Part 2 of 2)
Table 6 Test Pins
7 of 51
Name/Description
Name/Description
May 7, 2008