m36p0r9060e0 STMicroelectronics, m36p0r9060e0 Datasheet
m36p0r9060e0
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m36p0r9060e0 Summary of contents
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... Security – 64 bit unique device number – 2112 bit user programmable OTP Cells 100,000 Program/erase cycles per block Common Flash Interface (CFI) July 2006 M36P0R9060E0 FBGA TFBGA107 (ZAC) Block locking – All Blocks locked at power-up – Any combination of Blocks can be locked with zero latency – ...
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... PSRAM Configuration Register Enable (CR 2.17 Deep Power-Down input (DPD 2.18 V Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DDF 2.19 V Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CCP 2.20 V Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DDQ 2.21 V Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PPF 2.22 V Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/ M36P0R9060E0 ) . . . . . . . . . . . . . . . . . . . . . 11 ...
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... M36P0R9060E0 6 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3/23 ...
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... List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 7. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4/23 M36P0R9060E0 ...
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... M36P0R9060E0 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. TFBGA connections (top view through package Figure 3. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. TFBGA 107 8x11mm - 9x12 active ball array, 0.8mm pitch, package outline . . . . . . . . . . 19 5/23 ...
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... Summary description 1 Summary description The M36P0R9060E0 combines two memory devices in a Multi-Chip Package: 512-Mbit Multiple Bank Flash memory (the M58PR512J) 64-Mbit PSRAM (the M69KB096AM) The purpose of this document is to describe how the two memory components operate with respect to each other. It must be read in conjunction with the M58PRxxxJ and M69KB096AM datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed ...
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... M36P0R9060E0 Table 1. Signal names (1) A0-A24 DQ0-DQ15 V DDQ V PPF V DDF V CCP WAIT NC DU Flash Memory DPD F PSRAM A22-A24 are Address Inputs for the Flash memory component only. Address Inputs ...
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... DQ8 DQ2 DQ10 DQ0 DQ1 DQ3 DQ9 DQ11 DDF DDQ M36P0R9060E0 CCP V SS DPD DDF A21 A11 A22 A12 A13 E P A10 A15 L A20 A8 A14 ...
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... M36P0R9060E0 2 Signal descriptions See Figure 1., Logic diagram connected to this device. 2.1 Address inputs (A0-A24) Addresses A0-A21 are common inputs for the Flash memory and PSRAM components. Addresses A22 and A24 are inputs for the Flash memory component only. The Address Inputs select the cells in the Flash memory array to access during Bus Read operations. ...
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... Lock-Down is enabled and the protection status of the Locked Refer to the M58PRxxxJ datasheet, for the value DD2 , the device is in normal operation. Exiting Reset mode the IH M36P0R9060E0 , and Reset is High the Flash memory are deselected, the , Lock-Down is disabled IH , the IH , the ...
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... M36P0R9060E0 2.11 PSRAM Chip Enable input (E The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted (V ), the device is disabled, and goes automatically in low-power Standby mode or Deep IH Power-down mode, according to the RCR (Refresh Configuration Register) setting. 2.12 PSRAM Write Enable (W Write Enable, W ...
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... Program/Erase algorithm is completed. 12/ CCP DDQ gives an absolute protection against Program or Erase, PPLK enables these functions (see the M58PRxxxJ datasheet for the relevant it acts as a power supply pin. In this condition V PPH M36P0R9060E0 ) V is seen as a control input. In this PPF PPF must be ...
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... M36P0R9060E0 2.22 V Ground the common ground reference for all voltage measurements in the Flashmemory SS (core and I/O Buffers) and PSRAM chips. It must be connected to the system ground. Note: Each Flash memory device in a system should have their supply voltage (V the program supply voltage V (high frequency, inherently low inductance capacitors should be as close as possible to the package) ...
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... Figure 3. Functional block diagram A22-A24 A0-A21 14/ DDF PPF 512 Mbit RP F Flash Memory CCP Mbit G P PSRAM M36P0R9060E0 for the Flash memory F DPD F WAIT DQ0-DQ15 DDQ Ai10995 ...
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... M36P0R9060E0 Table 2. Main operating modes (2) Operation ( Flash Bus ( Read Flash Bus ( Write Flash Address Latch Flash Output Disable Flash Standby Flash Reset ...
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... DDF V PSRAM Supply Voltage CCP V Input/Output Supply Voltage DDQ V Flash Memory Program Voltage PPF I Output Short Circuit Current O t Time for V VPPH 16/23 Parameter at V PPF PPH M36P0R9060E0 Value Unit Min Max –30 85 °C –30 85 °C –55 125 °C –0.2 2.45 V –1.0 3.00 V –0.2 2 ...
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... M36P0R9060E0 5 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4., Operating and AC measurement operating conditions in their circuit match the operating conditions when relying on the quoted parameters ...
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... Sampled only, not 100% tested. Please refer to the M58PRxxxJ and M69KB096AM datasheets for further DC and AC characteristics values and illustrations. 18/23 DEVICE UNDER TEST CCP (1) Parameter Test Condition OUT M36P0R9060E0 V /2 CCQ R OUT C L AI06162a Min Max – 14 – 14 Unit pF pF ...
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... M36P0R9060E0 6 Package mechanical In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ...
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... Stacked TFBGA107 8x11mm - 9x12 active ball array, 0.8mm pitch, package data Symbol ddd 20/23 millimeters Typ Min Max 1.20 0.20 0.85 0.35 0.30 0.40 8.00 7.90 8.10 6.40 0.10 11.00 10.90 11.10 8.80 0.80 0.80 1.10 0.40 M36P0R9060E0 inches Typ Min Max 0.047 0.008 0.033 0.014 0.012 0.016 0.315 0.311 0.319 0.252 0.004 0.433 0.429 0.437 0.346 0.031 0.031 0.043 0.016 ...
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... M36P0R9060E0 7 Part numbering Table 7. Ordering information scheme Example: Device Type M36 = Multi-Chip Package (Flash + PSRAM) Flash 1 Architecture P = Multi-Level, Multiple Bank, Large Buffer Flash 2 Architecture Die Operating Voltage DDF CCP Flash 1 Density 9 = 512 Mbits Flash 2 Density Die RAM 1 Density ...
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... Document revision history Date 28-Nov-2005 20-Jul-2006 22/23 Revision 1 Initial release. Document status promoted to full Datasheet. PSRAM part changed. Flash memory component specifications 2 updated to latest version of M58PRxxxJ datasheet (V Table 3). H9 ball changed (top view through package). M36P0R9060E0 Changes changed in PP Figure 2: TFBGA connections ...
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... M36P0R9060E0 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...