scn68681 NXP Semiconductors, scn68681 Datasheet
scn68681
Available stocks
Related parts for scn68681
scn68681 Summary of contents
Page 1
... SCN68681 Dual asynchronous receiver/transmitter (DUART) Product data Supersedes data of 1998 Sep 04 INTEGRATED CIRCUITS 2004 Mar 02 ...
Page 2
... In addition, a flow control capability is provided to disable a remote DUART transmitter when the buffer of the receiving device is full. Also provided on the SCN68681 are a multipurpose 6-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control ...
Page 3
... OP6 10 DTACKN 11 RxDB TxDB OP1 15 OP3 INTRN Figure 1. Pin Configurations PARAMETER Product data SCN68681 PLCC 29 28 PIN/FUNCTION 16 OP5 31 OP2 17 OP7 32 OP0 TxDA RxDA X1/CLK 22 GND RESETN 24 INTRN ...
Page 4
... RECEIVE HOLDING REG (3) RECEIVE SHIFT REGISTER MR1, 2 CRA SRA CHANNEL B (AS ABOVE) INPUT PORT CHANGE OF STATE DETECTORS (4) IPCR ACR OUTPUT PORT FUNCTION SELECT LOGIC OPCR OPR Figure 2. Block Diagram 4 Product data SCN68681 TxDA RxDA TxDB RxDB 6 IP0-IP5 8 OP0-OP7 V CC GND SD00108 ...
Page 5
... Pin has an internal V device supplying current Power Supply supply input. CC GND I Ground. 2004 Mar 02 NAME AND FUNCTION pull-up device supplying current. 5 Product data SCN68681 CC CC pull-up CC pull-up device CC pull-up CC ...
Page 6
... floated X1/CLK floated X1/CLK floated 0 +70 C version – +85 C version 6 Product data SCN68681 LIMITS UNIT UNIT Min Typ Max – – 0 – – V 2.5 – – – – V – ...
Page 7
... If set-up time is violated, DTACKN may be asserted as shown, or may be asserted 1 clock cycle later. 8. Operation to 0 MHz is assured by design. Minimum test frequency is 2.0 MHz. 2004 Mar 5 PARAMETER PARAMETER 7 7 Product data SCN68681 LIMITS UNIT UNIT 3 Min Typ Max 200 – – – ...
Page 8
... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) BLOCK DIAGRAM The SCN68681 DUART consists of the following eight major sections: data bus buffer, operation control, interrupt control, timing, communications Channels A and B, input port and output port. Refer to the Block Diagram. Data Bus Buffer The data bus buffer provides the interface between the external and internal data buses ...
Page 9
... OPERATION Transmitter The SCN68681 is conditioned to transmit data when the transmitter is enabled through the command register. The SCN68681 indicates to the CPU that it is ready to accept a character by setting the TxRDY bit in the status register. This condition can be programmed to generate an interrupt request at OP6 or OP7 and INTRN ...
Page 10
... See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B” in application notes elsewhere in this publication 2004 Mar 02 should program the mode register prior to loading the corresponding data bits into the THR. ...
Page 11
... CSRA RECEIVER CLOCK SELECT CSRB CSRB See Text NOTE: * See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B” in application notes elsewhere in this publication BIT 7 BIT 6 CRA MISCELLANEOUS COMMANDS ...
Page 12
... MR1A[4:3], and the polarity of the forced parity bit if the ‘force parity’ mode is programmed. It has no effect if the ‘no parity’ mode is programmed. In the special multidrop mode it selects the polarity of the A/D bit. 12 Product data SCN68681 BIT 2 BIT 1 BIT 0 DELTA DELTA DELTA ...
Page 13
... For a character lengths of 5 bits, 1-1/ stop bits can be programmed in increments of 1/16 bit. The receiver only checks for a ‘mark’ condition at the center of the first stop bit position (one bit time after the last data bit, or after the parity bit is enabled), in all cases. 13 Product data SCN68681 ...
Page 14
... IP4-1X assuming the inactive state. CRA[2] – Enable Channel A Transmitter Enables operation of the Channel A transmitter. The TxRDY status bit will be asserted. 14 Product data SCN68681 ACR[ Baud Rate ACR[ IP2-16X IP2-16X IP2-1X IP2-1X ACR[ Baud Rate ACR[ ...
Page 15
... This field programs the OP4 output to provide one of the following: 0: The complement of OPR[4]. 1: The Channel A receiver interrupt output which is the complement of ISR[1]. When in this mode OP4 acts as an open-drain output. Note that this output is not masked by the contents of the IMR. 15 Product data SCN68681 ...
Page 16
... They are cleared when the IPCR is read by the CPU. A read of the IPCR also clears ISR[7], the input change bit in the interrupt status register. The setting of these bits can be programmed to generate an interrupt to the CPU. 16 Product data SCN68681 CLOCK SOURCE External (IP2)* TxCA – 1x clock of Channel A transmitter TxCB – 1x clock of Channel B ...
Page 17
... On power-up and after reset, the counter/timer runs in timer mode and can only be restarted. Because it cannot be shut off or stopped, and runs continuously in timer mode recommended that at initialization, the output port, OP3, should be masked off through the OPCR[3: until the C/T is programmed to the desired operational state. 17 Product data SCN68681 . Note that 16 ...
Page 18
... CTUR and CTLR. IVR – Interrupt Vector Register This register contains the interrupt vector. The register is initialized to H‘0F’ by RESET. The contents of the register are placed on the data bus when the DUART responds to a valid interrupt acknowledge cycle. 18 Product data SCN68681 ...
Page 19
... SD00109 t CSC RWS CSW CSD t DAL t DCR t DAT Figure 4. Bus Timing (Read Cycle) t CSC RWS CSD t DCW t DAT Figure 5. Bus Timing (Write Cycle) 19 Product data SCN68681 t RWH DAH SD00110 t RWH t CSW DAH SD00111 ...
Page 20
... INPUT) RxD 2004 Mar 02 t CSC CSD t DAL t t DCR DAH t DAT Figure 6. Interrupt Cycle Timing OLD DATA t PD Figure 7. Port Timing t t RXS RXH Figure 8. Receive Timing 20 Product data SCN68681 t DF SD00112 NEW DATA SD00113 SD00114 ...
Page 21
... OL 1 INTERRUPT OUTPUT V Figure 10. Interrupt Timing 1 BIT TIME ( CLOCKS) t TXD TxD t TCS Figure 11. Transmit Timing 21 Product data SCN68681 +5V R1: 100K - 1Meg (See design note C2: 0-5pF + (STRAY < 5pF) 1K CLOCK TO OTHER CHIPS 74LS04 SCN2681 X1 TO THE REST OF THE DUART CIRCUITS ...
Page 22
... BREAK D3 START D4 STOP BREAK BREAK Figure 13. Transmitter Timing STATUS DATA D5 WILL D2 BE LOST Figure 14. Receive Timing 22 Product data SCN68681 SD00093 WILL D6 NOT BE TRANSMITTED OPR( SD00118 D6, D7, D8 WILL BE LOST STATUS DATA STATUS DATA D3 D4 RESET BY COMMAND SD00119 ...
Page 23
... Also, if the transmitter, 23 Product data SCN68681 BIT 9 ADD#2 1 BIT 9 BIT 9 ADD#2 1 ...
Page 24
... Each read on address H‘2’ will toggle the baud rate test mode. When in the BRG test mode, the baud rates change as shown to the left. This change affects all receivers and transmitters on the DUART. See “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B” ...
Page 25
... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) DIP40: plastic dual in-line package; 40 leads (600 mil) 2004 Mar 02 25 Product data SCN68681 SOT129-1 ...
Page 26
... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) PLCC44: plastic leaded chip carrier; 44 leads 2004 Mar 02 26 Product data SCN68681 SOT187-2 ...
Page 27
... Product data (9397 750 12996). Supersedes data of 1998 Sep 04 (9397 750 04364). Modifications: Remove all references to 40-pin cerdip package (product discontinued). _2 19980904 Product specification (9397 750 04364). ECN 853-1083 19970 of 04 September 1998. Supersedes data of 1995 May 01. _1 19950501 2004 Mar 02 27 Product data SCN68681 ...
Page 28
... Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Fax: + 24825 Document order number: 28 Product data SCN68681 Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 03-04 9397 750 12996 ...