scn68652 NXP Semiconductors, scn68652 Datasheet - Page 18

• Manufacturer Part Number: scn68652
• Description: Multi-protocol Communications Controller Mpcc
• Manufacturer: NXP Semiconductors

Philips Semiconductors
TIMING DIAGRAMS
1995 May 01
Multi-protocol communications controller (MPCC)
NOTES:
1. SYNC may be 5 to 8 bits and will contain parity bit as specified.
2. TxA goes high relative to TxC rising edge after TSOM has been set and TxE has been raised.
3. TxBE goes low relative to DBEN falling edge on the first write transfer into TDSR. It is reasserted 1 TxC time before the first bit of the transmitted SYNC/FLAG. TxBE then goes
low relative to DBEN falling edge when writing into TDSR
character, except in BOP mode when the CRC is to be sent as the next character (see Transmit Timing–End of Message).
DBEN
TxSO
TxBE
TxC
TxE
TxA
SET TSOM
3
(Continued)
TxSO
RxSI
MARK
RxC
TxC
2
H
and/or TDSR
TxD
Figure 11. Timing Diagrams (cont.)
TRANSMIT – START OF MESSAGE
Figure 12. Timing Diagrams (cont.)
LOAD 1st CHAR
t
CLK0
t
CLK1
t
L
RxS
. It is reasserted on the rising edge of the TxC that corresponds to the transmission of the last bit of each
CLOCK
1/f
SYNC/FLAG
t
RxH
RESET TSOM
8 TxC
18
t
CLK1
t
CLK0
1
1
SCN2652/SCN68652
SD00066
1ST CHAR
LOAD 2nd CHAR
Product specification
SD00067