scn26562 NXP Semiconductors, scn26562 Datasheet

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scn26562

Manufacturer Part Number
scn26562
Description
Dual Universal Serial Communications Controller Duscc
Manufacturer
NXP Semiconductors
Datasheet

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Philips Semiconductors
DESCRIPTION
The Philips Semiconductors SCN26562 Dual Universal Serial
Communications Controller (DUSCC) is a single-chip MOS-LSI
communications device that provides two independent,
multi-protocol, full-duplex receiver/transmitter channels in a single
package. It supports bit-oriented and character-oriented (byte count
and byte control) synchronous data link controls as well as
asynchronous protocols. The SCN26562 interfaces to synchronous
bus MPUs and is capable of program-polled, interrupt driven,
block-move or DMA data transfers.
The operating mode and data format of each channel can be
programmed independently. Each channel consists of a receiver, a
transmitter, a 16-bit multi-function counter/timer, a digital
phase-locked loop (DPLL), a parity/CRC generator and checker, and
associated control circuits. The two channels share a common bit
rate generator (BRG), operating directly from a crystal or an external
clock, which provides 16 common bit rates simultaneously. The
operating rate for the receiver and transmitter of each channel can
be independently selected from the BRG, the DPLL, the
counter/timer, or from an external 1X or 16X clock, making the
DUSCC well suited for dual-speed channel applications. Data rates
up to 4Mbits per second are supported.
The transmitter and receiver each contain a four-deep FIFO with
appended transmitter command and receiver status bits and a shift
register. This permits reading and writing of up to four characters at
a time, minimizing the potential of receiver overrun or transmitter
underrun, and reducing interrupt or DMA overhead. In addition, a
flow control capability is provided to disable a remote transmitter
when the FIFO of the local receiving device is full.
Two modem control inputs (DCD and CTS) and three modem
control outputs (RTS and two general purpose) are provided.
Because the modem control inputs and outputs are general purpose
in nature, they can be optionally programmed for other functions.
This document contains the electrical specifications for the
SCN26562. See SCN26562/SCN68562 User’s Guide for complete
functional description.
FEATURES
General Features
1995 May 1
Dual full-duplex synchronous/asynchronous receiver and
transmitter
Multiprotocol operation
– BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,
– COP: BISYNC, DDCMP
– ASYNC: 5–8 bits plus optional parity
Four character receiver and transmitter FIFOs
0 to 4Mbit/sec data rate
Programmable bit rate for each receiver and transmitter selectable
from:
– 16 fixed rates: 50 to 38.4k baud
– One user-defined rate derived from programmable
– External 1X or 16X clock
– Digital phase-locked loop
Dual universal serial communications controller (DUSCC)
etc.
counter/timer
1
Asynchronous Mode Features
Parity and FCS (frame check sequence LRC or CRC) generation
and checking
Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester
Programmable channel mode: full- and half-duplex, auto-echo, or
local loopback
Programmable data transfer mode: polled, interrupt, DMA, wait
DMA interface
– Single- or dual-address dual transfers
– Half- or full-duplex operation
– Automatic frame termination on counter/timer terminal count or
Interrupt capabilities
– Vector output (fixed or modified by status)
– Programmable internal priorities
– Maskable interrupt conditions
Multi-function programmable 16-bit counter/timer
– Bit rate generator
– Event counter
– Count received or transmitted characters
– Delay generator
– Automatic bit length measurement
Modem controls
– RTS, CTS, DCD, and up to four general purpose pins per
– CTS and DCD programmable auto-enables for Tx and Rx
– Programmable interrupt on change of CTS or DCD
On-chip oscillator for crystal
TTL compatible
Single +5V power supply
Character length: 5 to 8 bits
Odd or even parity, no parity, or force parity
Up to two stop bits programmable in 1/16-bit increments
1X or 16X and Tx clock factors
Parity, overrun, and framing error detection
False start bit detection
Start bit search 1/2-bit time after framing error detection
Break generation with handshake for counting break characters
Detection of start and end of received break
Character compare with optional interrupt on match
Transmits up to 4Mbit/sec data rate Receives up to 2Mbit/sec data
rate
DMA EOPN input
channel
Product specification
SCN26562
853-0307 15179

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scn26562 Summary of contents

Page 1

... Because the modem control inputs and outputs are general purpose in nature, they can be optionally programmed for other functions. This document contains the electrical specifications for the SCN26562. See SCN26562/SCN68562 User’s Guide for complete functional description. FEATURES General Features ...

Page 2

... Detection and notification of received end of message CRC generation and checking SDLC loop mode capability V = +5V +5 Serial Data Rate = 4Mbps Maximum SCN26562C4N48 SCN26562C4A52 PARAMETER Product specification SCN26562 = + DWG # DWG # SOT240-1 SOT238-3 RATING UNIT 0 to +70 C -65 to +150 C –0.5 to +7.0 V –0 ...

Page 3

... GPO1BN 18 TxDRQBN GPO2BN/RTSBN 19 CTSBN/LCBN 27 EOPN WRN CEN RDN 25 RESETN 26 GND Figure 1. Pin Configurations 3 Product specification SCN26562 PLCC 34 33 PIN FUNCTION 27 CEN 28 WRN 29 EOPN CTSAN/LCAN 36 TxDRQAN/ GPO2AN/RTSAN 37 RTxDRQAN/ GPO1AN 38 TxDAKAN/ GPI2AN ...

Page 4

... DECODE R/W DECODE DMA CONTROL CCRA/B PCRA/B RSRA/B TRSRA/B ICTSRA/B GSR CMR1A/B CMR2A/B OMRA/B DUSCC LOGIC Figure 2. Block Diagram 4 Product specification SCN26562 CHANNEL MODE AND TIMING A/B DPLL CLK MUX A/B DPLLA/B BRG COUNTER TIMER A/B C/T CLK MUX A/B CTCRA/B CTPRHA/B CTPRLA/B CTHA/B CTLA/B TRANSMIT A/B TRANS CLK ...

Page 5

... Channel A (B) transmitter DMA service request, general purpose output or request-to-send. Channel A (B) receiver/transmitter DMA acknowledge or general purpose input 1. Channel A (B) transmitter DMA acknowledge or general purpose input 2. DMA transfer complete. Channel A (B) request-to-send or Sync detect. Power input. Signal and power ground. 5 Product specification SCN26562 ...

Page 6

... Figure 3. Reset Timing 6 Product specification SCN26562 LIMITS UNIT UNIT Min Typ Max 0.8 V 0.4 V 2 0.5 V 0.5 2.4 V 0.0 mA –5.5 1 –100 100 A –40 A – –5 A –25 A –120 A – 275 LIMITS SCN26562C2 UNIT UNIT Min Max 1.2 s SD00205 ...

Page 7

... RDHDDI RYZDDV 1 Figure 4. Read Cycle LIMITS SCN26562C4 Min Max 10 0 150 275 280 300 100 0 160 10 160 75 7 Product specification SCN26562 t CEHCEL SD00206 SCN26562C2 UNIT UNIT Min Max 150 275 ns 300 ns ns 310 100 170 170 ...

Page 8

... WRLADI t WRLWRH t WRHWRL t t WDVWRH WRHWDI 1 Figure 5. Write Cycle LIMITS SCN26562C4 Min Max 300 100 275 160 150 160 10 8 Product specification SCN26562 t CEHCEL SD00207 SCN26562C2 UNIT UNIT Min Max 310 ns 100 ns 275 170 ns 150 ns 170 ...

Page 9

... Figure 7. Output Port Timing SCN26562C4 Min 9 Product specification SCN26562 SERVICE ROUTINE Cleared through software A C SD00208 LIMITS SCN26562C2 UNIT UNIT Max Min Max ns 280 280 ns 150 150 WRHGOV NEW DATA SD00209 LIMITS SCN26562C2 UNIT UNIT Max Min Max 300 300 ns ...

Page 10

... Product specification SCN26562 SD00210 SCN26562C2 UNIT UNIT Min Max 20 ns 100 ns SD00211 SCN26562C2 UNIT UNIT Typ Max 14.7456 16.0 MHz 4.0 MHz 2.5 MHz 2.5 MHz ...

Page 11

... SILRCH t RCHSIH t t RXVRCH RCHRXI Figure 11. Receive Timing LIMITS SCN26562C4 Min Max 50 120 50 10 100 50 300 11 Product specification SCN26562 SD00212 SCN26562C2 UNIT UNIT Min Max 240 ns 435 SD00213 SCN26562C2 UNIT UNIT Min Max 130 100 ns 50 300 ns ...

Page 12

... WRN high to EOPN input high WRHEIH 1995 May 1 t WRLEOL t WRLTRH t EILWRH Figure 12. Transmit Dual Address DMA Timing SCN26562C4 Min Product specification SCN26562 t WRHEOZ A t WRHEIH SD00214 LIMITS SCN26562C2 UNIT UNIT Max Min Max ns 320 320 ns 225 225 ns 225 225 ...

Page 13

... RDN low to EOPN output low RDLEOL t RDN high to EOPN output high impedance RDHEOZ 1995 May 1 t RDLEOL Figure 13. Receive Dual Address DMA Timing SCN26562C4 Min 13 Product specification SCN26562 t RDLRRH A t RDHEOZ SD00215 LIMITS SCN26562C2 UNIT UNIT Max Min Max 320 320 ns 300 300 ns 225 225 ns ...

Page 14

... WDVTAH TAHWDI t Figure 14. DMA-Transmit Single Address Mode SCN26562C4 Min 100 250 Product specification SCN26562 t TAHEIH t EILTAH t TAHEOF TALEOL SD00216 LIMITS SCN26562C2 UNIT UNIT Max Min Max 100 ns 250 ns ns 250 250 170 170 ns 200 200 ...

Page 15

... RAHRAL RALRRH t RALEOL t RAHDDI t RAHDDF Figure 15. DMA-Receive Single Address Mode SCN26562C4 Min 160 250 10 15 Product specification SCN26562 t RAHEOF SD00217 LIMITS UNIT UNIT SCN26562C2 Max Min Max ns 160 ns 250 320 320 ns 200 200 ns 225 225 ns 225 225 125 125 ns ...

Page 16

... M t RWHIRH Figure 16. Interrupt Timing SCN26562C4 Min Max 450 450 400 400 400 Figure 17. Command Timing Product specification SCN26562 V +0. SD00218 LIMITS SCN26562C2 UNIT UNIT Min Max 450 ns 450 ns 400 ns 400 ns 400 ns SD00219 SD00220 ...

Page 17

... Dual universal serial communications controller (DUSCC) IRQN RDYN EOPN ALL OTHER OUTPUTS 150pF NOTE: All C includes 50pF stray capacitance, L i.e 150pF = 100pF discrete +50pF stray. L 1995 May 1 2. 50pF 820 +5.0V 150pF 50pF Figure 19. Test Conditions for Outputs 17 Product specification SCN26562 710 +5.0V SD00221 ...

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