k4s161622e Samsung Semiconductor, Inc., k4s161622e Datasheet - Page 13

• Manufacturer Part Number: k4s161622e
• Description: 1m X 16 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4S161622E
DEVICE OPERATIONS (Continued)
DQM OPERATION
The DQM is used to mask input and output operations. It works
similar to OE during read operation and inhibits writing during
write operation. The read latency is two cycles from DQM and
zero cycle for write, which means DQM masking occurs two
cycles later in read cycle and occurs in the same cycle during
write cycle. DQM operation is synchronous with the clock. The
DQM signal is important during burst interruptions of write with
read or precharge in the SDRAM. Due to asynchronous nature
of the internal write, the DQM operation is critical to avoid
unwanted or incomplete writes when the complete burst write is
not required. Please refer to DQM timing diagram also.
PRECHARGE
The precharge operation is performed on an active bank by
asserting low on CS, RAS, WE and A
bank to be precharged. The precharge command can be
asserted anytime after t
command in the desired bank. t
number of clock cycles required to complete row precharge is
calculated by dividing t
to the next higher integer. Care should be taken to make sure
that burst write is completed or DQM is used to inhibit writing
before precharge command is asserted. The maximum time any
bank can be active is specified by t
bank activate command. At the end of precharge, the bank
enters the idle state and is ready to be activated again. Entry to
Power down, Auto refresh, Self refresh and Mode register set
etc. is possible only when both banks are in idle state.
AUTO PRECHARGE
The precharge operation can also be performed by using auto
precharge. The SDRAM internally generates the timing to satisfy
t
latency. The auto precharge command is issued at the same
time as burst read or burst write by asserting high on A
burst read or burst write by asserting high on A
left active until a new command is asserted. Once auto
precahrge command is given, no new commands are possible to
that particular bank until the bank achieves idle state.
BOTH BANKS PRECHARGE
Both banks can be precharged at the same time by using pre-
charge all command. Asserting low on CS, RAS, and WE with
high on A
requirement, performs precharge on both banks. At the end of
t
in idle state.
RAS
RP
after performing precharge to all the banks, both banks are
(min) and "t
10
/AP after both banks have satisfied t
RP
" for the programmed burst length and CAS
RP
RAS
with clock cycle time and rounding up
(min) is satisfied from the bank active
RP
is defined as the minimum
RAS
10
/AP with valid BA of the
(max). Therefore, each
10
/AP, the bank is
RAS
10
/AP. If
(min)
AUTO REFRESH
The storage cells of SDRAM need to be refreshed every 32ms
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the rows.
An auto refresh command is issued by asserting low on CS,
RAS and CAS with high on CKE and WE. The auto refresh com-
mand can only be asserted with both banks being in idle state
and the device is not in power down mode (CKE is high in the
previous cycle). The time required to complete the auto refresh
operation is specified by t
clock cycles required can be calculated by driving t
clock cycle time and them rounding up to the next higher integer.
The auto refresh command must be followed by NOP's until the
auto refresh operation is completed. Both banks will be in the
idle state at the end of auto refresh operation. The auto refresh
is the preferred refresh mode when the SDRAM is being used
for normal data transactions. The auto refresh cycle can be per-
formed once in 15.6us or a burst of 2048 auto refresh cycles
once in 32ms.
SELF REFRESH
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for data
retention and low power operation of SDRAM. In self refresh
mode, the SDRAM disables the internal clock and all the input
buffers except CKE. The refresh addressing and timing are
internally generated to reduce power consumption.
The self refresh mode is entered from both banks idle state by
asserting low on CS, RAS, CAS and CKE with high on WE.
Once the self refresh mode is entered, only CKE state being low
matters, all the other inputs including the clock are ignored in
order to remain in the self refresh mode.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP's for
a minimum time of t
begin normal operation. If the system uses burst auto refresh
during normal operation, it is recommended to use burst 2048
auto refresh cycles immediately after exiting in self refresh
mode.
RFC
before the SDRAM reaches idle state to
RFC
(min). The minimum number of
CMOS SDRAM
Rev 1.1 Jan '03
RFC
with