k4s161622e Samsung Semiconductor, Inc., k4s161622e Datasheet - Page 6

• Manufacturer Part Number: k4s161622e
• Description: 1m X 16 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4S161622E
AC OPERATING TEST CONDITIONS
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Notes :
CAS Latency
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
Col. address to col. address delay
Mode Register Set cycle time
Number of valid output
data
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Output
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
(Fig. 1) DC Output Load Circuit
rounding off to the next higher integer. Refer to the following clock unit based AC conversion table
870
Parameter
Parameter
CAS Latency=3
CAS Latency=2
3.3V
50pF
1200
t
t
t
t
t
Symbol
t
t
t
t
RAS(max)
t
t
RRD(min)
RCD(min)
t
CCD(min)
MRS(min)
RAS(min)
RDL(min)
CDL(min)
BDL(min)
RC
CC(min)
RP(min)
V
V
CL
OH
OL
(
min
(DC) = 0.4V, I
(V
(DC) = 2.4V, I
)
DD
= 3.3V 0.3V, T
5.5
10
3
3
3
7
-55
10
10
2
3
3
7
OL
OH
= 2mA
= -2mA
10
3
6
3
3
7
A
-60
= 0 to 70 C)
10
tr / tf = 1 / 1
2
2
2
5
7
See Fig. 2
2.4 / 0.4
Value
1.4
1.4
Output
Version
10
3
7
3
3
7
100
-70
2
1
1
1
1
2
2
1
10
2
2
2
5
7
(Fig. 2) AC Output Load Circuit
3
8
3
3
6
9
-80
10
2
2
2
5
7
Z0=50
CMOS SDRAM
10
3
2
2
5
7
Rev 1.1 Jan '03
-10
12
2
2
2
4
6
Unit
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Vtt=1.4V
Unit
ea
ns
us
50
ns
50pF
V
V
V
Note
2, 5
1
1
1
1
1
2
2
4