k4s161622e Samsung Semiconductor, Inc., k4s161622e Datasheet - Page 2

• Manufacturer Part Number: k4s161622e
• Description: 1m X 16 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4S161622E
512K x 16Bit x 2 Banks Synchronous DRAM
FEATURES
• 3.3V power supply
• LVTTL compatible with multiplexed address
• Dual banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system
• Burst Read Single-bit Write operation
• DQM for masking
• Auto & self refresh
• 15.6us refresh duty cycle (2K/32ms)
FUNCTIONAL BLOCK DIAGRAM
clock
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
ADD
CLK
LCKE
* Samsung Electronics reserves the right to change products or specification without notice.
CLK
LRAS
CKE
Bank Select
LCBR
CS
LWE
RAS
Timing Register
LCAS
CAS
Latency & Burst Length
GENERAL DESCRIPTION
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
ORDERING INFORMATION
Programming Register
K4S161622E-TC55
WE
K4S161622E-TC60
K4S161622E-TC70
K4S161622E-TC80
K4S161622E-TC10
Data Input Register
The K4S161622E is 16,777,216 bits synchronous high data
Column Decoder
512K x 16
512K x 16
Part NO.
L(U)DQM
LWCBR
MAX Freq.
183MHz
166MHz
143MHz
125MHz
100MHz
CMOS SDRAM
Rev 1.1 Jan '03
LDQM
Interface Package
LVTTL
DQi
LWE
LDQM
TSOP(II)
50