sri512 STMicroelectronics, sri512 Datasheet - Page 16

• Manufacturer Part Number: sri512
• Description: 13.56-mhz Short-range Contactless Memory Chip With 512-bit Eeprom And Anti-collision Functions
• Manufacturer: STMicroelectronics

Memory mapping
4.2
16/50
Figure 14. WRITE_BLOCK update in reload mode (binary format)
32-bit binary counters
The two 32-bit binary counters located at block addresses 5 and 6, respectively, are used to
count down from 2
the update of a counter if the new value is lower than the previous one. This feature allows
the application to count down by steps of 1 or more. The initial value in the counter is
FFFF FFFFh. When the value displayed is 0000 0000h, the counter is empty and cannot be
reloaded. The counter is updated by issuing the WRITE_BLOCK command to block address
5 or 6, depending on which counter is to be updated. The WRITE_BLOCK command writes
the new 32-bit value to the counter block address.
counters operate.
The counter programming cycles are protected by automated antitearing logic. This function
allows the counter value to be protected in case of power down within the programming
cycle. In case of power down, the counter value is not updated and the previous value
continues to be stored.
Blocks 5 and 6 can be write-protected using the OTP_Lock_Reg bits (block 255). Once a
block has been protected, its contents cannot be modified. A protected counter block
behaves like a ROM block.
Figure 15. Binary counter (addresses 5 to 6)
Previous data stored in block
Data to be written
New data stored in block
Block
Address
5
6
b31
MSb
32
(4096 million) to 0. The SRI512 uses dedicated logic that only allows
b31
1
1
1
...
...
...
1
1
1
32-bit Binary Counter
32-bit Binary Counter
b16 b15 b14
1
1
1
32-bit Block
0
1
1
1
1
1
Figure 16
0
0
0
1
1
1
b8 b7
shows examples of how the
1
1
1
1
0
0
1
0
0
LSb
b0
1
1
1
Description
Count down
0
1
1
Counter
1
1
1
SRI512
ai12384
ai07659
1
1
1
b0