saa4700 NXP Semiconductors, saa4700 Datasheet - Page 3

• Manufacturer Part Number: saa4700
• Description: Vps Dataline Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
Dataline 16
The information in dataline 16
consists of fifteen 8-bit words; the
total information content is shown in
Table 1; and the organization of
transmitted bytes is shown in Table 2.
Out of the fifteen possible 8-bit words
the SAA4700 extracts words 5 and 11
to 14. The contents of these words
can be read via the built-in I
interface. The circuit is fully
transparent, thus each bit is
transferred without modification with
only the sequence of words being
changed. Words 11 to 14
March 1991
handbook, full pagewidth
VPS dataline processor
470 pF
CVBS
to V P
4.7
k
8.2 k
4.7 nF
nF
22
75 k
(2%)
4.7 nF
1 nF
13
17
2
1
PHASE DETECTOR
SEPARATOR
5 MHz VCO AND
SAA4700
REGENERATOR
SLICER
SYNC
2
DATA
PLL WITH
C-bus
CLOCK
5
0.1
F
line 16
CSO
data
are transmitted first followed by
word 5.
By evaluating the sliced sync signal
the circuit can identify the beginning
of dataline 16 in the first field. The
dataline decoder stage releases the
start code detector. When a correct
start code is detected (for timing of
start code detection see Fig.3) words
5 and 11 to 14 are decoded, checked
for biphase errors and stored in a
register bank. If no biphase error has
occurred, the contents of the register
bank are transferred to a second
register bank by the data valid control
signal. If the system has been
addressed, this transfer will be
VCS
Fig.1 Block diagram and test circuit.
6
clock pulse
LINE 16 DECODER
FIELD SELECTOR
14
CONTROLLER
INPUT
11
(test line 16)
3
TIME BASE
data
CONTROLLER
4
6
OUTPUT
POWER-ON RESET
DAV
3
REFERENCE
12
VOLTAGES
delayed until the next start or stop
condition of the I
received.
The last bit of correct information on
the dataline remains available until it
is read via the I
stored information has been read it is
considered to be no longer valid and
the internal new data flag is reset.
Subsequently, if the circuit is
addressed, the only VPS data that will
be sent back is ”FFF to F”. The same
conditions apply after power-up when
no data can be read out. New data is
available after reception of another
error-free dataline 16.
MULTIPLEXER
4
DATA LATCH
40-BIT DATA
0.1 F
5
REGISTER
40-BIT
15
CONTROL
I
16
2
Preliminary specification
C-BUS
8
2
external
C-bus. Once the
7
2
reset
C-bus has been
AD = LOW
V P
SAA4700
10
5 V
18
8
9
MEH095
n.c.
SCL
SDA