m470t5663eh3 Samsung Semiconductor, Inc., m470t5663eh3 Datasheet - Page 17

• Manufacturer Part Number: m470t5663eh3
• Description: Ddr2 Unbuffered Sodimm
• Manufacturer: Samsung Semiconductor, Inc.

SODIMM
13.3 Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the component datasheet)
DQ output access time from CK/CK
DQS output access time from CK/CK
Average clock HIGH pulse width
Average clock LOW pulse width
CK half pulse period
Average clock period
DQ and DM input hold time
DQ and DM input setup time
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS/DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
DQ/DQS output hold time from DQS
DQS latching rising transitions to associated clock edges
DQS input HIGH pulse width
DQS input LOW pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
MRS command to ODT update delay
Write postamble
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
Read postamble
Activate to activate command period for 1KB page size products tRRD
Activate to activate command period for 2KB page size products tRRD
Parameter
tAC
tDQSCK
tCH(avg)
tCL(avg)
tHP
tCK(avg)
tDH(base)
tDS(base)
tIPW
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tMOD
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
Symbol
Min(tCL(abs),
17 of 22
2* tAC(min)
tHP - tQHS
tCH(abs))
tAC(min)
- 0.25
2500
min
0.48
0.48
0.35
0.35
-400
-350
125
0.35
250
175
0.2
0.2
0.4
0.35
0.9
0.4
7.5
50
0.6
10
2
0
x
x
x
DDR2-800
tAC(max)
tAC(max)
tAC(max)
max
8000
0.52
0.52
0.25
200
300
400
350
0.6
1.1
0.6
12
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Min(tCL(abs),
2* tAC(min)
tHP - tQHS
tCH(abs))
tAC(min)
3000
-0.25
min
-450
-400
0.48
0.48
0.35
0.35
0.35
175
100
0.35
275
200
0.6
0.2
0.2
0.4
0.9
0.4
7.5
10
2
0
x
x
x
DDR2-667
tAC(max)
tAC(max)
tAC(max)
max
8000
0.52
0.52
0.25
450
400
340
240
0.6
1.1
0.6
12
Rev. 1.0 August 2008
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
DDR2 SDRAM
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Units
nCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ps
ps
ns
ns
6,7,8,21,28,31
6,7,8,20,28,31
5,7,9,23,29
5,7,9,22,29
Notes
35,36
35,36
35,36
18,40
18,40
18,40
19,41
19,42
4,32
4,32
40
40
37
13
38
39
30
30
30
32
10