hys64t128020edl-3s-c Qimonda, hys64t128020edl-3s-c Datasheet - Page 19

• Manufacturer Part Number: hys64t128020edl-3s-c
• Description: 200-pin So-dimm Ddr2 Sdram Modules Ddr2 Sdram So-dimm Sdram
• Manufacturer: Qimonda

26)
27)
28) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
29) 0 °C≤
30) 85 °C <
31) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
32)
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
34) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
35) For these parameters, the DDR2 SDRAM device is characterized and verified to support
36)
Rev. 1.02, 2007-10
11212006-D34H-5W6Z
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
t
the max column. {The less half-pulse width distortion present, the larger the
Examples: 1) If the system provides
provides
t
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
and 95 °C.
t
(
driving (
calculation is consistent.
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
and
+
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
and
+
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
t
t
QH
QHS
RPST
nRP
WTR
RPST
t
t
JIT.PER.MAX
JIT.DUTY.MAX
=
t
t
= RU{
accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual
JIT.PER.MAX
JIT.DUTY.MAX
is at lease two clocks (2 x
end point and
t
), or begins driving (
HP
T
CASE
T
t
RPRE
–
t
CASE
HP
t
t
RP
QHS
of 1420 ps into a DDR2–667 SDRAM, the DRAM provides
≤ 85 °C.
= 1.1 x
) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
= 0.6 x
/
≤ 95 °C.
= + 93 ps, then
t
, where:
CK.AVG
= + 93 ps, then
t
t
RPRE
CK.AVG
t
} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
CK.AVG
t
HP
begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
t
RPRE
is the minimum of the absolute half period of the actual input clock; and
+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
t
).
RPRE.MIN(DERATED)
t
t
RPST.MIN(DERATED)
CK
Figure 2
) independent of operation frequency.
t
HP
of 1315 ps into a DDR2–667 SDRAM, the DRAM provides
shows a method to calculate these points when the device is no longer driving (
=
=
t
RPRE.MIN
t
RPST.MIN
+
+
t
t
JIT.PER.MIN
JIT.DUTY.MIN
19
= 0.9 x
= 0.4 x
t
Method for calculating transitions and endpoint
QH
of 1080 ps minimum.
t
t
QH
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C
CK.AVG
t
CK.AVG
value is; and the larger the valid data eye will be.}
– 72 ps = + 2178 ps and
– 72 ps = + 928 ps and
t
nPARAM
SO-DIMM DDR2 SDRAM Module
= RU{
t
QH
t
QHS
t
t
of 975 ps minimum. 2) If the system
JIT.PER
JIT.DUTY
t
t
nRP
RP
t
PARAM
is the specification value under
= 15 ns, the device will support
= RU{
of the input clock. (output
t
t
of the input clock. (output
RPRE.MAX(DERATED)
RPST.MAX(DERATED)
/
t
CK.AVG
t
Internet Data Sheet
t
RP
HP
t
/
t
at the input is
JIT.DUTY.MIN
JIT.PER.MIN
t
}, which is in clock
CK.AVG
FIGURE 2
t
RPST
}, which is in
), or begins
=
=
= – 72 ps
= – 72 ps
t
t
RPRE.MAX
RPST.MAX