hys64t128020edl-3s-c Qimonda, hys64t128020edl-3s-c Datasheet - Page 4

• Manufacturer Part Number: hys64t128020edl-3s-c
• Description: 200-pin So-dimm Ddr2 Sdram Modules Ddr2 Sdram So-dimm Sdram
• Manufacturer: Qimonda

1.2
The
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C
family are small-outline DIMM modules “SO-DIMMs” with 30
mm height based on DDR2 technology. DIMMs are available
as non-ECC modules in128M × 64 (1GB), 256M × 64 (2GB)
in organization and density, intended for mounting into 200-
pin connector sockets.
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400S–555–12–F0" where 6400S
Rev. 1.02, 2007-10
11212006-D34H-5W6Z
Product Type
PC2-6400-555
HYS64T128020EDL–25F–C
HYS64T256020EDL–25F–C
PC2-6400-666
HYS64T128020EDL–2.5–C
HYS64T256020EDL–2.5–C
PC2-5300-444
HYS64T128020EDL–3–C
HYS64T256020EDL–3–C
PC2-5300-555
HYS64T128020EDL–3S–C
HYS64T256020EDL–3S–C
PC2-4200-444
HYS64T128020EDL–3.7–C
HYS64T256020EDL–3.7–C
means Small-Outline DIMM modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS) latency
=5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the latest JEDEC SPD Revision 1.2 and produced
on the Raw Card "F".
1)
Description
Compliance Code
1GB 2R×16 PC2–6400S–555–12–A0
2GB 2R×8 PC2–6400S–555–12–F0
1GB 2R×16 PC2–6400S–666–12–A0
2GB 2R×8 PC2–6400S–666–12–F0
1GB 2R×16 PC2–5300S–444–12–A0
2GB 2R×8 PC2–5300S–444–12–F0
1GB 2R×16 PC2–5300S–555–12–A0
2GB 2R×8 PC2–5300S–555–12–F0
1GB 2R×16 PC2–4200S–444–12–A0
2GB 2R×8 PC2–4200S–444–12–F0
Qimonda
2)
module
4
Ordering Information for RoHS Compliant Products
The memory array is designed with 1 Gbit Double-Data-Rate-
Two (DDR2) Synchronous DRAMs. Decoupling capacitors
are mounted on the PCB board. The DIMMs feature serial
presence detect based on a serial E
2-pin I
configuration data and are write protected; the second
128 bytes are available to the customer.
2
C protocol. The first 128 bytes are programmed with
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C
Description
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
SO-DIMM DDR2 SDRAM Module
2
SDRAM Technology
1Gbit (×16)
1Gbit (×8)
1Gbit (×16)
1Gbit (×8)
1Gbit (×16)
1Gbit (×8)
1Gbit (×16)
1Gbit (×8)
1Gbit (×16)
1Gbit (×8)
PROM device using the
Internet Data Sheet
TABLE 2