gs820h32aq-133 GSI Technology, gs820h32aq-133 Datasheet

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gs820h32aq-133

Manufacturer Part Number
gs820h32aq-133
Description
64k X 32 2m Synchronous Burst Sram
Manufacturer
GSI Technology
Datasheet
TQFP, QFP
Commercial Temp
Industrial Temp
Features
• FT pin for user configurable flow through or pipelined operation.
• Single Cycle Deselect (SCD) Operation.
• High Output Drive current.
• 3.3V +10%/-5% Core power supply
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
• Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• JEDEC standard 100-lead TQFP or QFP package.
Functional Description
Applications
The GS820H32A is a 2,097,152 bit high performance synchronous
SRAM with a 2 bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPU’s, the device now finds application in synchronous
SRAM applications ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/O’s, chip enables (E
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive edge triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Rev: 1.04 3/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Through
Pipeline
3-1-1-1
2-1-1-1
Flow
tCycle
tCycle
t
I
t
I
KQ
DD
KQ
DD
270mA
170mA
10.5ns
6.6ns
3.8ns
-150
9ns
245mA
120mA
7.25ns
9.7ns
15ns
-138
4ns
2M Synchronous Burst SRAM
240mA
120mA
7.5ns
15ns
10ns
-133
1
4ns
, E
2
, E
3
210mA
120mA
), address burst control
8.5ns
15ns
11ns
-117
4.5
180mA
120mA
10ns
15ns
12ns
-100
5ns
64K x 32
1/23
150mA
12.5ns
95mA
20ns
18ns
6ns
-66
Flow Through / Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode pin/bump (Pin 14 in the TQFP, bump 1F in the FP-
BGA). Holding the FT mode pin/bump low, places the RAM in Flow
through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipelined Mode,
activating the rising edge triggered Data Output Register.
The GS820H32A is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are also
available. SCD SRAMs pipeline deselect commands one stage less
than read commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in the
input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS820H32A operates on a 3.3V power supply and all inputs/
outputs are 3.3V and 2.5V compatible. Separate output power (V
pins are used to de-couple output noise from the internal circuit.
Pipelined Reads
GS820H32AT/Q-150/138/133/117/100/66
© 2000, Giga Semiconductor, Inc.
150Mhz - 66Mhz
3.3V & 2.5V I/O
9ns - 18ns
3.3V VDD
DDQ
)
E

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gs820h32aq-133 Summary of contents

Page 1

... Functional Description Applications The GS820H32A is a 2,097,152 bit high performance synchronous SRAM with a 2 bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPU’s, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support ...

Page 2

GS820H32A 100 Pin TQFP and QFP Pinout 100 DDQ ...

Page 3

TQFP Pin Description Pin Location 37, 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49 52, 53, 56, 57, 58, 59, 62, 63 68, 69, 72, 73, 74, 75, 78 ...

Page 4

GS820H32A Block Diagram Register A0- LBO ADV CK ADSC ADSP Power Down ZZ Control Rev: 1.04 3/2000 Specifications ...

Page 5

Mode Pin Functions Mode Name Pin Name State Burst Order Control Output Register Control Power Down Control Note: There are pull up devices on LBO and FT pins and a pull down device on and ZZ pin, so those input ...

Page 6

Synchronous Truth Table Operation Address Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...

Page 7

Simplified State Diagram Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low. 2. The upper portion of the diagram assumes active use of only the Enable (E and that ADSP is ...

Page 8

Simplified State Diagram with G Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make ...

Page 9

Absolute Maximum Ratings (All voltages reference Symbol Description V Voltage on V Pins Voltage in V Pins DDQ DDQ V Voltage on Clock Input Pin CK V Voltage on I/O Pins I/O V ...

Page 10

... Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP) Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper- ature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87. 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1. ...

Page 11

AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...

Page 12

Operating Currents Parameter Test Conditions Device Selected; Operating All other inputs Current Output open Standby 0.2V DD Current Device Deselected; Deselect All other inputs Current Operating Currents Parameter Test ...

Page 13

AC Electrical Characteristics Parameter Symbol Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Clock to Output Valid Flow- Thru Clock to Output Invalid Clock to Output in Low-Z ...

Page 14

Write Cycle Timing Single Write ADSP ADSC ADV -An 0 WR1 Hi ...

Page 15

Flow Through Read Cycle Timing Single Read ADSP ADSC ADV -An RD1 tOLZ ...

Page 16

Flow Through Read-Write Cycle Timing Single Read ADSP ADSC ADV tS tH A0-An RD1 tOE G tKQ Hi-Z ...

Page 17

Pipelined SCD Read Cycle Timing Single Read ADSP ADSC ADV RD1 Hi ...

Page 18

Pipelined SCD Read - Write Cycle Timing Single Read ADSP ADSC ADV -An 0 RD1 ...

Page 19

... Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention ...

Page 20

GS 820H32A Output Driver Characteristics 120.0 100.0 Pull Down Drivers 80.0 60.0 40.0 20.0 0.0 -20.0 -40.0 -60.0 Pull Up Drivers -80.0 -100.0 -120.0 -140.0 -0 Rev: 1.04 3/2000 Specifications cited are subject to change without ...

Page 21

TQFP and QFP Package Drawing Symbol Description A1 A2 Body Thickness b c Lead Thickness D Terminal Dimension D1 Package Body E Terminal Dimension E1 Package Body Notes: 1. All dimensions ...

Page 22

... GS820H32AQ-5 64K x 32 GS820H32AQ-6 64K x 32 GS820H32AQ-150I 64K x 32 GS820H32AQ-138I 64K x 32 GS820H32AQ-133I 64K x 32 GS820H32AQ-4I 64K x 32 GS820H32AQ-5I 64K x 32 GS820H32AQ-6I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS820H32AT-100IT. ...

Page 23

Revision History Types of Changes DS/DateRev. Code: Old; Format or Content New GS82032 Rev 1.03 2/ 2000D;GS820321.04 3/2000E Rev: 1.04 3/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS820H32AT/Q-150/138/133/117/100/66 Revisions • First Release of ...

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