psd935g2 STMicroelectronics, psd935g2 Datasheet - Page 78

• Manufacturer Part Number: psd935g2
• Description: Configurable Memory System On A Chip For 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

Microcontroller Interface – PSD935G2 AC/DC Parameters
(3.0 V to 3.6 V Versions)
Power Down Timing
V
PSD935G2
Reset Pin Timing
NOTE: 1. t
NOTE: 1. Vstbyon is measured at V
NOTE: 1. RESET will not abort Flash programming/erase cycles.
stbyon
Symbol
Symbol
t
t
Symbol
t
t
t
t
t
t
BVBH
BXBL
NLNH
OPR
NLNH-PO
NLNH-A
LVDV
CLWH
2. RESET will abort Flash programming or erase cycle.
Timing
CLCL
is the CLKIN clock period.
V stby Detection to V stbyon Output
High
V stby Off Detection to V stbyon
Output Low
Warm RESET Active Low Time (Note 1)
RESET High to Operational Device
Power On Reset Active Low Time
Warm RESETActive Low Time
(Note 2)
ALE Access Time from
Power Down
Maximum Delay from APD Enable
to Internal PDN Valid Signal
(3.0 V to 3.6 V Versions)
Parameter
Parameter
(3.0 V to 3.6 V Versions)
(3.0 V to 3.6 V Versions)
Parameter
CC
ramp rate of 2 ms.
Using CLKIN Input
Conditions
Conditions
Conditions
(Note 1)
(Note 1)
Min
Min
Min
300
15
25
1
-90
*
PSD9XX Family
t
Max
CLCL
128
Typ
Typ
20
20
(µs) (Note 1)
Min
-12
Max
Max
300
Max
135
Unit
Unit
Unit
ms
µs
µs
ns
µs
µs
ns
ns
77