ne56604-42d NXP Semiconductors, ne56604-42d Datasheet - Page 10

• Manufacturer Part Number: ne56604-42d
• Description: System Reset With Built-in Watchdog Timer
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Timing diagram
The timing diagram shown in Figure 20 depicts the operation of the
device. Letters indicate events on the TIME axis.
A: At start-up ‘A’, the V
the RESET voltage initially rises, but then abruptly returns to a LOW
state. This is due to V
activates the internal bias circuitry, asserting RESET.
B: Just before ‘B’, the C
by, and coincident to, V
this level the device is in full operation. The RESET output continues
to rise as V
C: At ‘C’, V
has ramped up to its upper detect level. At this point, the device
removes the hold on the resets. RESET goes HIGH while RESET
goes LOW. Also, an internal ramp discharge transistor activates,
discharging C
In a microprocessor-based system these events remove the reset
from the microprocessor, allowing it to function normally. The system
must send clock signals to the Watchdog Timer often enough to
prevent C
signals from being generated. Each clock signal discharges C
C–D: Midway between ‘C’ and ‘D’, the CLK signals cease allowing
the C
reset signals are generated (RESET goes LOW; RESET goes
HIGH). The device attempts to come out of reset as the C
is discharged and finally does come out of reset when CLK signals
are re-established after two attempts of C
2003 Oct 15
System reset with built-in Watchdog timer
T
C
RESET
RESET
Tthresh
voltage to ramp up to its RESET threshold at ‘D’. At this time,
0.8 V
CLK
V
V
V
CC
C
T
SH
SL
T
CC
from ramping up to the C
CC
T
rises above V
.
A
is above the undervoltage detect threshold, and C
CC
CC
reaching the level (RESET 0.8 V) that
CC
T
reaching the threshold level of V
B
voltage starts to ramp up. This is caused
SH
and RESET voltages begin to rise. Also
. This is normal.
t
PR
T
threshold, to prevent reset
T
t
CLK
.
C
t
WDM
Figure 20. Timing diagram.
T
SH
voltage
. At
T
D
.
T
10
TIME
E–F: Immediately before ‘E’, falling V
to sag. CLK signals are still being received, C
operating range, and reset signals are not output. V
sag until the V
reset signals are generated (RESET goes LOW; RESET goes
HIGH).
At ‘E’, V
However, C
reaches the V
G: The reset outputs are released at ‘G’ when C
upper threshold level again. After ‘G’, normal CLK signals are
received, but at a lower frequency than those following event ‘C’.
The frequency is above the minimum frequency required to keep the
device from outputting reset signals.
G–H: At ‘H’, V
no reset signals are output. At event ‘H’, the V
causing RESET to also fall.
J: At event ‘J’, V
threshold point is reached, and at that level reset signals are output
(RESET to a LOW state, and RESET to a HIGH state). As the V
voltage falls lower, the RESET voltage falls lower.
K: At event ‘K’, the V
normal internal circuit bias is no longer able to maintain a RESET,
and as a result may exhibit a slight rise to something less than 0.8 V.
As V
CC
t
WDR
CC
decays even further, RESET also decreases to zero.
E
starts to rise, and the RESET voltage rises with V
T
F
voltage does not start to ramp up until ‘F’, when V
SH
SL
CC
upper threshold.
undervoltage threshold is reached. At that time,
CC
is normal, CLK signals are being received, and
sags to the point where the V
CC
voltage has deteriorated to a level where
G
CC
causes the RESET signal
NE56604-42
T
CC
H
is within normal
starts falling,
T
J
SL
CC
reaches the
undervoltage
continues to
Product data
SL01283
K
CC
CC
.
CC