lis3l02ds STMicroelectronics, lis3l02ds Datasheet
lis3l02ds
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lis3l02ds Summary of contents
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... EMBEDDED SELF TEST ■ HIGH SHOCK SURVIVABILITY DESCRIPTION The LIS3L02DS is a tri-axis digital output linear ac- celerometer that includes a sensing element and an IC interface able to take the information from the sensing element and to provide the measured acceleration signals to the external world through an I2C/SPI serial interface ...
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... LIS3L02DS PIN DESCRIPTION N° Pin Internally not connected 6 GND 0V supply 7 Vdd Power supply 8 RDY/INT Data ready/inertial wake-up interrupt 9 SDO SPI Serial Data Output 10 SDA/ I2C Serial Data (SDA) SDI/ SPI Serial Data Input (SDI) SDO 3-wire Interface Serial Data Output (SDO) ...
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... T = 25°C Full-scale = 2g BW=56Hz T = 25°C -50 Full-scale = 2g Best fit straight line X, Y axis Full-scale = 2g BW=56Hz Best fit straight line Z axis Full-scale = 2g BW=56Hz Dec factor = 128 Dec factor = 64 Dec factor = 32 Dec factor = 8 LIS3L02DS 1 Max. Unit Typ. 3 1.5 mA µ 1150 Hz ±2.0 g ±6.0 ...
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... LIS3L02DS ABSOLUTE MAXIMUM RATING Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ...
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... Figure 1. Equivalent electrical circuit C R ps1 s1 S1x C s1x s2x S2x C R ps2 ps1 s1 S1y C s1y s2y S2y C R ps2 ps1 s1 S1z C s1z s2z S2z C R ps2 s2 LIS3L02DS rot 5/18 ...
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... The acceleration data may be accessed through an I2C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The LIS3L02DS features a Data-Ready signal (DRY) which indicated when a new set of measured accel- eration data is available thus simplifying data synchronization in digital system employing the device itself. ...
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... Interface Serial Data Output (SDO) SDO SPI Serial Data Output (SDO) 2.1 I2C Serial Interface The LIS3L02DS I2C is a bus slave. The I2C is employed to write the data into the registers whose content can also be read back. 2 The relevant I C terminology is given in the table below Table 2 ...
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... LIS3L02DS knowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data has been received. 2 The I C embedded inside the Gengine ASIC behaves like a slave device and the following protocol must be adhered to ...
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... DI(7:0) (write mode). This is the data that will be written into the device (MSb first). – bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 LIS3L02DS DI0 9/18 ...
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... LIS3L02DS 2.2.2 SPI Read Figure 3. SPI Read protocol CS SPC SPDI RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 SPDO The SPI Read command consists is performed with 16 clocks pulses: – bit 0: READ bit. The value is 1. – bit 1-7: address AD(6:0). This is the address field of the indexed register. ...
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... LIS3L02DS Size Comment (Bit) Reserved 8 Loaded at boot 8 Loaded at boot 8 Loaded at boot 8 Loaded at boot 8 Loaded at boot 8 Loaded at boot Reserved 8 8 Reserved Reserved ...
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... LIS3L02DS 4 REGISTERS DESCRIPTION The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. 4.1 OFFSET_X (16h) OX7 OX7, OX0 Digital Offset Trimming for X-Axis 4.2 OFFSET_Y (17h) OY7 DOY7, DOY0 Digital Offset Trimming for Y-Axis 4.3 OFFSET_Z (18h) OZ7 ...
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... RDY pad; 1: int req on RDY pad) DRDY Enable Data-Ready generation SIM SPI Serial Interface Mode selection (0: 4-wire interface; 1: 3-wire interface) DAS Data Alignement Selection (0: 12 bit right justified bit left justified) PD0 DF1 DF0 ST x BOOT IEN LIS3L02DS Zen Yen Xen DRDY SIM DAS 13/18 ...
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... LIS3L02DS 4.9 WAKE_UP_CFG (23h) x LIR Latch interrupt request (1: interrupt request latched) MZH Mask Z High Interrupt (1: enable int req on measured accel. value higher than preset threshold) MZL Mask Z Low Interrupt (1: enable int req on measured accel. value lower than preset threshold) MYH Mask Y High Interrupt (1: enable int req on measured accel ...
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... X axis acceleration data MSb 4.15 OUTY_L (2Ah) YD7 YD7, YD0 Y axis acceleration data LSb ZOR YOR XOR ZYXDA XD6 XD5 XD4 XD3 . XD13 XD12 XD11 YD6 YD5 YD4 YD3 LIS3L02DS ZDA YDA XDA XD2 XD1 XD0 XD10 XD9 XD8 YD2 YD1 YD0 15/18 ...
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... LIS3L02DS 4.16 OUTY_H (2Bh) When reading the register in “12 bit right justified” mode the most significant bits (7:4) are replaced with bit 3 (i.e. YD15- YD12=YD11, YD11, YD11, YD11) YD15 YD14 YD15, YD8 Y axis acceleration data MSb 4.17 OUTZ_L (2Ch) ZD7 ZD7, ZD0 Z axis acceleration data LSb 4.18 OUTZ_H (2Dh) When reading the register in “ ...
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... H 10.0 10.65 0.394 h 0.25 0.75 0.010 k 0˚ (min.), 8˚ (max.) L 0.40 1.27 0.016 B 0.10mm .004 Seating Plane inch MECHANICAL DATA TYP. MAX. 0.104 0.012 0.100 0.0200 0.013 0.614 0.299 0,050 0.419 0.030 0.050 LIS3L02DS OUTLINE AND SO24 h x 45˚ SO24 17/18 ...
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... LIS3L02DS Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...