w66910 Winbond Electronics Corp America, w66910 Datasheet - Page 22

• Manufacturer Part Number: w66910
• Description: Te Mode Isdn S/t-controller With Microprocessor Interface
• Manufacturer: Winbond Electronics Corp America

Send Single Pulses
A 2 KHz , isolated pulse with alternating polarities is sent.
Layer 1 Reset
A layer 1 reset command forces the transmission of INFO 0 and disables the S line awake detector. Thus activation from NT is
not possible. There is no indication in reset state. The reset state is disabled only with ECK command.
TABLE 7.2 LAYER 1 COMMAND CODES
Command
Enable clock
Layer 1 reset
Send continuous pulses
Send single pulses
Activate request at priority 8
Activate request at priority 10
Enable analog loopback
Deactivate layer 1
TABLE 7.3 LAYER 1 INDICATION CODES
Indication
Clock Enabled
Deactivate request downstream DRD
Level detected
Activate request downstream
Test indication
Awake test indication
Activate indication with priority
class 1
Activate indication with priority
class 2
Clock disabled
7.2.3.2 State Transition Diagrams
The followings are the state transition diagrams, which implement the activation/deactivation state matrix in I.430 (TABLE
5/I.430). The "command" and "s receive" entries in each state octagon keep the state, the "indication" and "s transmit" entries in
each state octagon are the state outputs. For example, at "F3 Deactivated with clock" state, the layer 1 will stay at this state if the
command is "ECK" and the INFO 0 is received on S interface. At this state, it provides "CE" indication to the microprocessor
and transmits INFO 0 on S interface. The "AR8/10" command causes transition to F4 and non-INFO 0 signal causes transition to
Symbol
ECK
RST
SCP
SSP
AR8
AR10
EAL
DRC
Symbol
CE
LD
ARD
TI
ATI
AI8
AI10
CD
Code
0000
0001
0100
0010
1000
1001
1010
1111
Code
0111
0000
0100
1000
1010
1011
1100
1101
1111
Description
Enable internal clocks or to stop reset
Layer 1 reset
Send continuous pulses at 96 kHz
Send isolated pulses at 2 kHz
Activate layer 1 and set D channel priority level to 8
Activate layer 1 and set D channel priority to 10
Enable analog loopback
Deactivate layer 1 and disable internal clocks
Descriptions
Internal clocks are enabled
Deactivation request by S interface, i.e INFO 0 received
Signal received, receiver not synchronous
INFO 2 received
Analog loopback activated or continuous zeros or single zeros
transmitted
Level detected during test function
INFO 4 received, D channel priority is 8 or 9
INFO 4 received, D channel priority is 10 or 11
Layer 1 deactivated, internal clocks are disabled
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W66910 PCI ISDN S/T-Controller
Publication Release Date:
Data Sheet
Revision 1.0
Feb,2001