pcd3312cp NXP Semiconductors, pcd3312cp Datasheet - Page 11

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pcd3312cp

Manufacturer Part Number
pcd3312cp
Description
Dtmf/modem/musical-tone Generators
Manufacturer
NXP Semiconductors
Datasheet

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8
The I
(SDA) and a serial clock line (SCL), both of which are bi-directional. Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus
is not busy.
8.1
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period
of the clock pulse as changes in the data line at this time will be interpreted as control signals.
8.2
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as the stop condition (P).
1996 Nov 21
DTMF/modem/musical-tone generators
I
2
2
C-BUS INTERFACE
C-bus is for two-way communication between different ICs or modules. It uses only two lines, a serial data line
Bit transfer (see Fig.7)
Start and stop conditions (see Fig.8)
SDA
SCL
START condition
SDA
SCL
S
Fig.8 Start and stop conditions.
data valid
data line
stable;
Fig.7 Bit transfer.
11
allowed
change
of data
STOP condition
PCD3311C; PCD3312C
P
MBC621
MBC622
SDA
SCL
Product specification

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