s5935qrc Applied Micro Circuits Corporation (AMCC), s5935qrc Datasheet - Page 16

• Manufacturer Part Number: s5935qrc
• Description: Pci Product
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

S5935 – PCI Product
Add-On Bus Operation Registers
The third and last register group consists of the Add-
On Operation Registers, shown in Table 3. This group
of eighteen 32-bit (DWORD) registers is accessible to
the Add-On Local bus. These are the main registers
through which the Add-On logic configures S5935
operation and communicates with the PCI Local bus.
These registers encompass the Add-On bus Mail-
boxes, Add-On FIFO, DMA Address/Count Registers
(when Add-On initiated Bus Mastering), Pass-Thru
Registers and Status/Control registers.
Table 2. PCI Operation Registers
16
Outgoing Mailbox Register 1 (OMB1)
Outgoing Mailbox Register 2 (OMB2)
Outgoing Mailbox Register 3 (OMB3)
Outgoing Mailbox Register 4 (OMB4)
Incoming Mailbox Register 1 (IMB1)
Incoming Mailbox Register 2 (IMB2)
Incoming Mailbox Register 3 (IMB3)
DS1527
PCI Operation Registers
Address
Offset
0Ch
00h
04h
08h
10h
14h
18h
Table 2. PCI Operation Registers
Non-Volatile Memory Interface
The S5935 contains a set of PCI Configuration Regis-
ters. These registers can be initialized with default
values or with designer specified values contained in
an external nvRAM. The nvRAM can be either a serial
(2 Kbytes, maximum) or a byte-wide device (64
Kbytes, maximum).
Incoming Mailbox Register 4 (IMB4)
FIFO Register Port (bidirectional) (FIFO)
Master Write Address Register (MWAR)
Master Write Transfer Count Register (MWTC)
Master Read Address Register (MRAR)
Master Read Transfer Count Register (MRTC)
Mailbox Empty/Full Status Register (MBEF)
Interrupt Control/Status Register (INTCSR)
Bus Master Control/Status Register (MCSR)
PCI Operation Registers
Revision 1.02 – June 27, 2006
AMCC Confidential and Proprietary
Data Book
Address
Offset
1Ch
2Ch
3Ch
20h
24h
28h
30h
34h
38h