s5935qrc Applied Micro Circuits Corporation (AMCC), s5935qrc Datasheet - Page 48

• Manufacturer Part Number: s5935qrc
• Description: Pci Product
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

S5935 – PCI Product
BUILT-IN SELF-TEST REGISTER (BIST)
Figure 17. Built-In Self Test Register
Table 24. Built-In Self-Test Register
48
Register Name
Address Offset
Power-up value
Boot-load
Attribute
Size
Bit
5:4
3:0
7
6
DS1527
BIST Capable. This bit indicates that the Add-On device supports a built-in self-test when a one is returned. A zero
should be returned if this self test feature is not desired. This field is read only from the PCI interface.
Start BIST. Writing a 1 to this bit indicates that the self-test should commence. This bit can only be written when bit 7 is
a 1. When bit 6 becomes set, an interrupt is issued to the Add-On interface. Other than through the reset pin, Bit 6 can
only be cleared by a write to this element from the Add-On bus interface as outlined in Section 6.5. The PCI bus spec-
ification requires that this bit be cleared within 2 seconds after being set, or the device will be failed.
Reserved. These bits are reserved. This field will always return zeros.
Completion Code. This field provides a method for detailing a device-specific error. It is considered valid when the Start
BIST field (bit 6) changes from 1 to 0. An all-zero value for the completion code indicates successful completion.
X
7
Built-in Self-Test
write only
0
6
0Fh
00h
External nvRAM/EPROM offset 04Fh
D7, D5-0 Read Only, D6 as PCI bus
8 bits
0
5
0
4
X
3
Description
The Built-In Self-Test (BIST) register permits the
implementation of custom, user-specific diagnostics.
This register has four fields as depicted in Figure 10.
Bit 7, when set signifies that this device supports a
built-in self test. When bit 7 is set, writing a 1 to bit 6
will commence the self test. In actuality, writing a 1 to
bit 6 produces an interrupt to the Add-On interface. Bit
6 will remain set until cleared by a write operation to
this register from the Add-On bus interface. When bit 6
is reset it is interpreted as completion of the self-test
and an error is indicated by a non-zero value for the
completion code (bits 3:0).
X
2
X
1
X
0
Revision 1.02 – June 27, 2006
AMCC Confidential and Proprietary
Bit
Value
User defined
Completion Code (RO)
Reserved (RO)
Start BIST (WO)
BIST Capable (RO)
Data Book