cx29600 Mindspeed Technologies, cx29600 Datasheet - Page 27
cx29600
Manufacturer Part Number
cx29600
Description
Optiphytm - M155 Sts-3 Sonet/sdh Multiplexer
Manufacturer
Mindspeed Technologies
Datasheet
1.CX29600.pdf
(219 pages)
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CX29600
CX29600 Data Sheet
Table 1-4. Pin Definitions (3 of 17)
29600-DSH-001-B
LRxPFP
LRxPFN
LTxData–
LTxData+
LTxClk–
LTxClk+
TxFrameOut
TxSDCC_Clk
TxLDCC_Clk
TxTstClk
Pin Label
Receive PLL Filter
(Positive)
Receive PLL Filter
(Negative)
Line Transmit Output
Negative Polarity
Line Transmit Output
Positive Polarity
Line Transmit Clock
Output Negative
Polarity
Line Transmit Clock
Output Positive
Polarity
Transmit Frame
Reference Output
Transmit Section
DCC Clock Output
Transmit Line DCC
Clock Output
Transmit 19.44 MHz
Clock Output
Signal Name
Mindspeed Technologies
AC19
AD19
AC21
No.
E4
E1
D1
C2
D2
C5
F4
Analog
Analog
PECL
PECL
PECL
PECL
Type
TTL
TTL
TTL
TTL
Diff
Diff
Diff
Diff
™
I/O
O
O
O
O
O
O
O
O
I
I
(1)
External RC network pins for PLL.
See
External RC network pins for PLL.
See
SONET/SDH formatted Line
Transmit Data.
Complement of the above PECL
Line Transmit Data.
622.08/155.52 MHz output
derived from one of three clock
sources: transmit clock
synthesizer, recovered receive
clock or the LTxClkI+/- Input. The
clock source is selected in bits 3
and 4 of the CLKREC register. It is
generally used for diagnostic
purposes.
Complement of the above PECL
Line Transmit Clock output.
8 kHz output derived from the
Transmit SONET/SDH frame. See
Section
192 kHz output clock used to
sampled the Transmit Section
DCC input data (TxSDCC_Dat).
See
576 kHz output clock used to
sample the Transmit Line DCC
input data (TxLDCC_Dat). See
Section
19.44 MHz test clock output
generated by the Transmit
Synthesizer.
Figure
Figure
Section
5.1.8.
2.4.3.15.
1.0 Product Description
Description
2-2.
2-2.
2.4.2.7.
1.5 Logic Diagram
1-13
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