cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 14

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

Table 1-1.
29380-DSH-001-B
XTIP[1:4]
XRING[1:4]
CLADI
REFCKI
CLK32
CLK1544
CLK2048
CLADO
HM
RAWMD[1:4]
Pin Label
Hardware Signal Definitions (2 of 5)
Transmit Tip
Transmit Ring
CLAD Input
Reference Clock
32 MHz Clock Output
T1 Clock Output
E1 Clock Output
CLAD Output
Hardware Mode
Raw Mode
Signal Name
Preliminary Information / Mindspeed Proprietary and Confidential
Mindspeed Technologies
I/O
I/O
O
O
O
O
I
I
I
I
P
P
Clock Rate Adapter (CLAD)
Hardware Control Signals
Complementary AMI transmitter line outputs for direct connection to transmit
transformer. Optionally, both outputs are three-stated when XOE is high.
CLAD input timing reference used to phase/frequency lock the CLAD outputs to an
input clock frequency selected in the range of 8 kHz to 32,768 kHz [CLAD_CR;
addr 02]. Systems which do not use CLADI should connect CLADI to ground. If
CLADI is selected as the reference, the CLAD timing reference automatically
switches to internal free-run operation if clock edges are not detected on CLADI
pin.
System must apply a 10 MHz ± 50 ppm (E1) or + 32 ppm (T1) clock signal to act
as the frequency reference for the internal numerically controlled oscillator (NCO).
REFCKI determines the frequency accuracy and stability of the CLAD output
clocks when operating in free-run mode
[CLAD_CR; addr 02]. REFCKI is the baseband reference for all CLAD/JAT
functions and is used internally to generate clocks of various frequency locked to
a selected receive or external clock.
Note: REFCKI is always required.
Fixed rate 32.768 MHz clock output provided by the CLAD. May be used by
framers, such as the CX28398 octal T1/E1 framer, to provide system timing
reference. CLK32 is not three-stated during RESET.
Fixed rate 1.544 MHz T1 line rate clock output provided by the CLAD. May be used
for TCLK or TACKI clock sources. This clock is locked to the selected CLAD timing
reference.
Fixed rate 2.048 MHz E1 line rate clock output provided by the CLAD. May be used
for TCLK or EACKI clock sources. This clock is locked to the selected CLAD timing
reference.
In Hardware Mode, CLADO is a fixed rate 8 kHz clock output provided by the
CLAD. In Host Mode, CLADO may be configured to operate at one of 14 different
clock frequencies [CSEL; addr 03] that include T1 or E1 line rates. CLADO is
typically programmed to supply system clocks that are phase-locked to the
selected receive or CLAD timing reference
[CLAD_CR; addr 02].
A high on HM places the device in Hardware Mode, enabling all hardware control
pin functions. A low on HM places the device in Host Mode, disabling some
hardware-mode-only pin functions and enabling the serial port signals on the dual
function pins listed below. The serial port signals allow serial host access to the
device registers. See the Host Serial Control Signals section of this table.
JSEL(1) / CS
JDIR / SCLK
Low selects receiver Raw mode. Applicable only in Hardware Mode. In Raw mode,
RPOSO and RNEGO represent the data slicer outputs, and RCKO is the logical OR
of RPOSO and RNEGO.
®
JSEL(2) / SDI
JATERR(1) / SDO
Definition
Pin Descriptions
6