cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 18

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

2.1
The CX28380 includes four identical T1/E1 transceiver channels and a common CLAD packaged in a 128-pin
MQFP carrier. It is designed to interface T1/E1 framers, or to operate as a stand-alone line interface for
synchronous or plesiochronous mappers and multiplexers. The CX28380 is ideal for high line density, short-haul
applications that require low power (3.3 V supply) operation. The configurable T1/E1 operation and common line
interface design allows support for single-board T1 and E1 designs.
Customer premise applications are supported by an on-chip JAT which conforms to AT&T pub 62411 and a
selectable transmit pulse shape which conforms to FCC Part 68, Pulse Option A. Selectable unipolar or bipolar
interface options and internal ZCS encoding and decoding are useful in many multiplexer and mapper applications.
In the simplest configuration, Hardware Mode, the device is controlled using dedicated hardware control pins. In
this mode, the four channels are configured globally to identical operating modes (T1, E1, transmit termination,
jitter attenuators, and so on). Each channel has device pins dedicated for channel control and status, such as
loopback controls and loss of signal indicators. Hardware Mode is selected by pulling the HM pin high.
Host Mode allows control of the device through a 4-line serial port. In this mode, all control and status functions can
be accessed using internal registers. Several additional features are also available in Host Mode, such as individual
channel operating mode configuration (T1/E1, transmit termination, jitter attenuators, etc.) and programmable
CLAD input and output frequencies. Host Mode is selected by grounding the HM pin.
The CX28380 incorporates printed circuit board testability circuits in compliance with IEEE Standard P1149.1a–
1993, IEEE Standard Test Access Port and Boundary–Scan Architecture, commonly known as JTAG (Joint Test
Action Group).
29380-DSH-001-B
Figure 2-1
Overview
illustrates a detailed block diagram.
Preliminary Information / Mindspeed Proprietary and Confidential
1
2.0 Circuit Description
Mindspeed Technologies
®
10