74HC/HCT173 Philips Semiconductors (Acquired by NXP), 74HC/HCT173 Datasheet - Page 2

• Manufacturer Part Number: 74HC/HCT173
• Description: Quad D-type Flip-flop; Positive-edge Trigger; 3-state
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT173 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT173 are 4-bit parallel load registers with
clock enable control, 3-state buffered outputs (Q
and master reset (MR).
When the two data enable inputs (E
data on the D
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
December 1990
t
f
C
C
PHL
max
Gated input enable for hold (do nothing) mode
Gated output enable control
Edge-triggered D-type register
Asynchronous master reset
Output capability: bus driver
I
Quad D-type flip-flop; positive-edge trigger; 3-state
I
PD
CC
f
f
C
V
For HCT the condition is V
SYMBOL
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
CC
PD
L
category: MSI
= output frequency in MHz
= input frequency in MHz
(C
PLH
= output load capacitance in pF
P
is used to determine the dynamic power dissipation (P
= supply voltage in V
L
D
= C
V
amb
CC
n
PD
inputs is loaded into the register
2
= 25 C; t
propagation delay
maximum clock frequency
input capacitance
power dissipation
capacitance per flip-flop
V
f
CP to Q
MR to Q
o
CC
) = sum of outputs
2
f
r
PARAMETER
i
n
= t
n
I
I
f
= GND to V
= GND to V
= 6 ns
(C
1
L
and E
V
CC
2
2
CC
) are LOW, the
CC
f
o
1.5 V
) where:
0
to Q
C
notes 1 and 2
L
3
= 15 pF; V
)
2
CONDITIONS
.
synchronously with the LOW-to-HIGH clock (CP)
transition. When one or both E
set-up time prior to the LOW-to-HIGH clock transition, the
register will retain the previous data. Data inputs and clock
enable inputs are fully edge-triggered and must be stable
only one set-up time prior to the LOW-to-HIGH clock
transition.
The master reset input (MR) is an active HIGH
asynchronous input. When MR is HIGH, all four flip-flops
are reset (cleared) independently of any other input
condition.
The 3-state output buffers are controlled by a 2-input NOR
gate. When both output enable inputs (OE
LOW, the data in the register is presented to the Q
outputs. When one or both OE
outputs are forced to a high impedance OFF-state. The
3-state output buffers are completely independent of the
register operation; the OE
clock and reset operations.
D
in W):
CC
= 5 V
17
13
88
3.5
20
HC
n
transition does not affect the
TYPICAL
n
n
inputs are HIGH one
inputs are HIGH, the
74HC/HCT173
17
17
88
3.5
20
Product specification
HCT
1
and OE
ns
ns
MHz
pF
pF
UNIT
n
2
) are