w89c840af Winbond Electronics Corp America, w89c840af Datasheet - Page 10

• Manufacturer Part Number: w89c840af
• Description: 100/10mbps Ethernet Controller
• Manufacturer: Winbond Electronics Corp America

VDD
GND
MMDIO
MCRS
MCOL
MRXDV
MRXER
MRXCLK
MRXD[3:0]
I/O
I
I
I
I
I
I
1,12,25,3
6,46,52,6
2,73,84,8
6,96,108,
119
2,14,20,3
7,47,53,6
107-104
100
101
102
95
98
99
-10 -
MII management data input/output.
This pin is used to transfer the MII control and status
information between PHY and MAC.
Carrier Sense Signal:
This shall be asserted by PHY device when media is
busy, and deasserted when media is idle. MCRS shall
keep asserted, even at the duration of a collision.
MII Collision detected:
This shall be asserted by the PHY device upon detecting
a collision happened over the medium. It will be asserted
and lasted until collision condition wholly vanishes.
MII Received data valid:
This pin is driven by PHY device. It will be asserted
when received data is coming and present, and
deasserted at the end of the frame. MRXDV is
synchronized with MRXCLK from PHY device.
MII Received data error:
This pin is driven by PHY device. It indicates a data
conversion error is detected by PHY device. The
assertion of MRXER should be lasted for longer than a
period of MRXCLK. When MRXER asserted,
W89C840AF will report a Receive Error detection and a
CRC
MII Received clock source:
This clock is from PHY device. It will be either 25Mhz
or 2.5Mhz receive clock, determined by auto-negotiation
device in PHY and supported by W89C840AF. The
minimun duty cycle at its high state or low state of
MRXCLK should be 35% of the nominal period under
all condition. PHY device should drive MRXCLK as a
continuous clock.
Received data pins:
This is driven by external 100/10 Mbps PHY. MRXD
should be syncronized with clock source MRXCLK and
valid only when MRXDV is valid. MRXD[0] is the least
significant bit.
Power supply pins.
Ground pins.
error.
Publication Release Date:October 2000
Revision 1.01
W89C840AF