w89c840af Winbond Electronics Corp America, w89c840af Datasheet - Page 20

• Manufacturer Part Number: w89c840af
• Description: 100/10mbps Ethernet Controller
• Manufacturer: Winbond Electronics Corp America

state machine will fetch the data in the host memory into the transmit FIFO. when the transmission DMA is started
up. All of the data fetched from the data buffer will be long word aligned before being queued into the transmission
FIFO. The driver program can inform the transmit DMA the location of the data to be transmitted in the host memory
and then the transmit DMA will fetch the data from that location directly. Because the address of the data may not
long word aligned, so that the transmit DMA need to align the data for passing the data to the MAC in a long word
aligned format. The aligned long word data, and then, is queued into the transmit FIFO. The transmission DMA will
not request the MAC to fetch the data in the FIFO for transmitting until the byte count of the data in the FIFO is
reach the threshold defined by C18/CNCR bit 14~20.
this implementation, the transmit DMA will pre-fetch the next packet data in the host memory after the current
packet data is moved into the transmit FIFO completely. Before starting to fetch the next packet data, the transmit
DMA will assert an interrupt if the transmit early interrupt is enabled. If there is no more packet to be transmitted,
the transmit DMA will report a buffer unavailable status and assert an interrupt if the transmit buffer unavailable
interrupt is enabled. After all of the current packet data in the transmit FIFO are transferred out by the MAC block,
the transmit DMA will try to fetch the next packet data again automatically if the transmit DMA is not fetching the
data from the host memory. A packet transmit interrupt will be asserted when the current packet is transmitted if
the packet transmitted interrupt is enabled.
transmit packet when the packet is successfully transmitted or is aborted due to excessive collision.
data in the host memory and then release the access right to the W89C840AF. Once the transmit DMA is turned
on, the DMA will transmit all of the packet out automatically. The inter-frame gap between these packets will be
specified by the MAC block for complying with the IEEE802.3u specification.
The transmission DMA is implemented a pre-fetch function for speeding the transmit performance. With
The transmit DMA will write back the current packet transmit status into the first descriptor of the current
For consecutively transmitting multiple packets, the software driver can previously program all the packet
The data to be transmitted is stored in the transmit data buffer in the host memory. The transmission DMA
data
buffer 1
data
buffer 2
data
buffer 3
data
buffer n
Tx
descriptor 1
Tx
descriptor 2
Tx
descriptor 3
Tx
descriptor n
PCI
data
PCI
master
long word
aligning buffer
-20 -
PCI slave
control
transmission
DMA
state machine
Publication Release Date:October 2000
Revision 1.01
2
FIFO
Kbytes
controls
from/to
MAC
data
to
MAC
W89C840AF