vsc055xkm-01 Maxim Integrated Products, Inc., vsc055xkm-01 Datasheet - Page 14

• Manufacturer Part Number: vsc055xkm-01
• Description: Enhanced I?c Backplane Controller
• Manufacturer: Maxim Integrated Products, Inc.

Table 1. CKSEL Settings (continued)
2.5
Revision 4.1
January 2008
The VSC055-01 device can operate at frequencies other than those listed in the above table and maintain
accurate fan speed and LED control frequencies, as well as continue to meet both the Standard mode
(100 kHz) and Fast mode (400 kHz) serial interface timings. Frequencies from 8.0 MHz to 12.5 MHz and
32.0 MHz to 75.0 MHz are allowable as long as they meet the AC timing requirements. For information on
AC timing requirements, see
The Clock Divider Control Register (CDC), located at FEh, can be programmed to override the divider
value selected by the CKSEL input pins and adjust the divided clock source used for the fan speed and
LED control logic. The pulse-width modulated outputs are not controlled by this logic and can vary based
on the input frequency. For examples of various frequency settings, based on both the CKSEL inputs and
the appropriate CDC register value,
Logic within the VSC055-01 synchronizes the divided clocks between devices attached to the same two-
wire serial bus with no more than 200 ns of skew when the fixed divider frequencies are used. Multiple
devices can then be used to drive different LEDs at the same frequency, providing a synchronized visible
indication. Devices attached to different two-wire serial busses can be synchronized by enabling the
SYNC# pin. This pin, which is connected to the SYNC# pin of all VSC055-01 devices in the system,
provides a sync pulse based on a programmable delay that is greater than the slowest selected LED flash
rate. For more information about the programmable capabilities of this feature, see
Control (CSC),”
Power-on Reset
Power-on reset (POR) is accomplished by the use of an internal POR cell. After power on, the serial
interface state machine always returns an idle state while waiting for a START condition to appear on the
SCL and SDA pins. A proper power-on reset sequence clears the serial interface state machine, the clock
generators, the control registers, the I/O control logic, and the port bypass control logic. The divided clocks
used for LED flash rate generation are also in a known state. Regardless of the effectiveness of the power-
on reset mechanism, it is strongly recommended that the control registers and the I/O control logic be
cleared through the Soft Reset register bit. This can be accomplished by writing a 80h to the BCT Register
(FCh), followed immediately by a STOP condition. This bit is self-resetting and does not require further
attention.
CKSEL2
VDD
VDD
VDD
page 111.
CKSEL1
VSS
VDD
VDD
“AC Characteristics,”
see“FEh: Clock Divider Control (CDC),”
CKSEL0
VDD
VDD
VSS
14 of 133
page 119.
Input Clock
53.125 MHz
33.33 MHz
50.0 MHz
Divider
÷4
÷6
÷6
page 113.
“FDh: Clock Select
Internal Clock
8.854 MHz
8.33 MHz
8.33 MHz
VSC055-01
Data Sheet