vsc055xkm-01 Maxim Integrated Products, Inc., vsc055xkm-01 Datasheet - Page 99

• Manufacturer Part Number: vsc055xkm-01
• Description: Enhanced I?c Backplane Controller
• Manufacturer: Maxim Integrated Products, Inc.

VSC055-01
Data Sheet
3.2.88 E0h-E7h: Bit Control Port 6 (BCP60-BCP67)
These eight registers function the same as the eight Bit Control Port 0 registers except that they relate to
the Port 6 I/O pins. In addition, the control of the individual I/O pins assigned to these registers can be
overridden by the PBC12, PBC13, PBC14, and PBC15 registers when port bypass control is required. For
information about the functionality of the Bit Control Port 0 registers, see
(BCP00-BCP07),”
The following table shows the bit assignments for the Bit Control Port 6 registers.
Register Name:
Address:
Reset Value:
Bit
7
6:5
Bit Label
PTE
BYP1-0
page 78.
BCP60-BCP67
E0h-E7h
0000_001Xb
Access
R/W
R/W
Description
Pulse Train Enable
This bit, along with the FS bits, enables one of eight pulse train circuits
controlled by the pulse train registers, PTC00 through PTC71 (70h through
7Fh), as the output drive function for this I/O pin.
When the PTE bit is set, the FS bits select one of eight pulse train circuits
instead of the normal fixed-rate LED flashing circuits or the normal output drive
mode. For the various LED drive control modes, see
After a reset or power on, this bit is cleared.
Bypass Select
These two bits determine the bypass function of the odd-numbered I/O pins
P0.7, P0.5, P0.3, and P0.1.
Setting either or both of these bits causes the I/O pin to be configured as an
output that reflects the input state of the corresponding even-numbered I/O
pins P0.6, P0.4, P0.2, and P0.0.
As an example, P0.1 can be configured as an output that follows the signal
applied to the P0.0 input. These two register bits only appear in the
odd-numbered bit control registers BCP07, BCP05, BCP03, and BCP01. For
the available output drive combinations, see
Note: These bits are only used when the bypass function is desired. They
should not be set when normal GPIO operation, PBC operation, or fan speed
monitoring are selected through the appropriate registers or through the use of
the FS, DD, and GPD bits. The PWM function (Port 0 only) and bypass function
are the highest priority controls for the appropriate I/O pin. The next highest
priorities are the PBC function (Port 3 through Port 6) and fan speed monitoring
(Port 1 and Port 2). The lowest priorities are the bit control features found in the
GPD, DD, and BCP registers.
Only one mode of operation should be enabled for each I/O pin at any time. If a
mode change is desired, first disable the existing mode, then enable the new
mode.
99 of 133
“80h-87h: Bit Control Port 0
Table 4,
Table 5,
page 80.
page 80.
January 2008
Revision 4.1