ST10R272L-B0 STMICROELECTRONICS [STMicroelectronics], ST10R272L-B0 Datasheet

ST10R272L-B0

Manufacturer Part Number

ST10R272L-B0

Description

16-BIT ROMLESS LOW VOLTAGE MCU WITH MAC

Manufacturer

STMICROELECTRONICS [STMicroelectronics]

Datasheet

1.ST10R272L-B0.pdf (4 pages)

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ST10R272L-B0

16-BIT ROMLESS LOW VOLTAGE MCU WITH MAC

ERRATA SHEET

1 INTRODUCTION

This errata sheet describes the functional and electrical problems known in the step B0 of the

ST10R272L-B0. This is the erratasheet of the ST10R272L datasheet version 1.2 of april

2000.

2 FUNCTIONAL PROBLEMS

The following malfunctions are known in this step:

2.1 ST_PWRDN.1: EXECUTION OF PWRDN INSTRUCTION WHILE NMI PIN IS HIGH

When PWRDN instruction is executed while NMI pin is at a high level, power-down mode

should not be entered, and the PWRDN instruction should be ignored. However, under the

conditions described below, the PWRDN instruction may not be ignored, and no further in-

structions are fetched from external memory, i.e. the CPU is in a quasi-idle state. This prob-

lem will only occur in the following situations:

1) the instructions following the PWRDN instruction are located in an external memory, and

a multiplexed bus configuration with memory tristate waitstate (bit MTTCx= 0) is used,

2) the instruction preceding the PWRDN instruction writes to external memory or an XPeriph-

eral (XRAM, CAN), and the instructions following the PWRDN instruction are located in ex-

ternal memory. In this case, the problem will occur for any bus configuration.

Note: the on-chip peripherals still work correctly: if the Watchdog Timer is not disabled, it will

reset the device upon an overflow. Interrupts and PEC transfers, however, can not be proc-

essed. If NMI is asserted low while the device is in this quasi-idle state, power-down mode is

entered.

No problem will occur if the NMI pin is low: the chip will normally enter power-down mode.

Workaround: Ensure that no instruction which writes to external memory or an XPeripheral

precedes the PWRDN instruction, otherwise insert e.g. a NOP instruction in front of PWRDN.

When a multiplexed bus with memory tristate waitstate is used, the PWRDN instruction

should be executed from internal RAM or XRAM.

Rev. 1.0

April 2000

1/4

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ST10R272L-B0 Summary of contents

Page 1

... ROMLESS LOW VOLTAGE MCU WITH MAC 1 INTRODUCTION This errata sheet describes the functional and electrical problems known in the step B0 of the ST10R272L-B0. This is the erratasheet of the ST10R272L datasheet version 1.2 of april 2000. 2 FUNCTIONAL PROBLEMS The following malfunctions are known in this step: 2 ...

Page 2

... ST10R272L-B0 Errata Sheet 2.2 ST_MAC.9: COCMP INSTRUCTION INVERTED OPERANDS According to the ST10 Family Programming Manual, the CoCmp instruction substracts a 40-bit signed operand from the 40-bit accumulator content (acc - op2\op1), and updates the N, Z and C flags in the MSW register, leaving the accumulator unchanged. ...

Page 3

... XPERs cannot be done as these would cause a conflict. Workaround: Use a Startup Configuration other than 8-bit multiplexed mode. If HOLD mode is entered (P6 following an 8-bit multiplexed mode access and if Xpershare is enabled, Xper accesses will cause a conflict on the internal XBUS xb_data [15:7] bus. Workaround: None. . ST10R272L-B0 Errata Sheet 3/4 ...

Page 4

... ST10R272L-B0 Errata Sheet 3 HISTORY OF FIXED FUNCTIONAL PROBLEMS OF THE ST10R272L: Functional Problem CPU.17 Arithmetic Overflow by DIVLU instruction TRAP_B.1 ATOMIC / EXTended sequences in Class B Hardware Trap Kfm_BR03 Pipeline conflict after CoStore operation Kfm_BR04 Wrong PSW value after byte instruction Kfm_BR05 Wrong result for BFLDL/BFLDH instructions CORE ...

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