hy5ps1g831alfp Hynix Semiconductor, hy5ps1g831alfp Datasheet - Page 18

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hy5ps1g831alfp

Manufacturer Part Number
hy5ps1g831alfp
Description
1gb Ddr2 Sdram
Manufacturer
Hynix Semiconductor
Datasheet
Rev. 0.7 / Oct. 2007
Note :
1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V (exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3 speed
2. IDD specifications are tested after the device is properly initialized
3. Input slew rate is specified by AC Parametric Test Condition
5. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with
4. IDD parameters are specified with ODT disabled.
6.
grade)
all combinations of EMRS bits 10 and 11.
Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks)
for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals not including masks or strobes.
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