hy5ps1g831alfp Hynix Semiconductor, hy5ps1g831alfp Datasheet - Page 26

• Manufacturer Part Number: hy5ps1g831alfp
• Description: 1gb Ddr2 Sdram
• Manufacturer: Hynix Semiconductor

Rev. 0.7 / Oct. 2007
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the
setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system
design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single
VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that
when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied
externally to VSS through a 20 ohm to 10 K ohm resistor to insure proper operation.
5. AC timings are for linear signal transitions. See System Derating for other signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They
7. All voltages referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal
reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full
voltage range specified.
may be guaranteed by device design or tester correlation.
CK/CK
DQS/DQS
DQ
DQS/
DQS
DQ
DM
CK
CK
DQS
DQS
t
CH
t
t
RPRE
DQS
DQS
WPRE
Figure -- Data output (read) timing
V
V
IL
IH
(ac)
(ac)
t
DMin
DS
t
t
CL
DQSQmax
D
Figure -- Data input (write) timing
t
DQSH
V
V
IH
IL
(ac)
(ac)
t
t
DMin
DS
QH
D
Q
t
DQSL
DMin
Q
D
t
DH
V
IH
V
(dc)
IL
(dc)
t
DQSQmax
DMin
Q
V
D
t
IL
DH
(dc)
V
IH
t
WPST
(dc)
HY5PS1G1631A(L)FP
HY5PS1G431A(L)FP
HY5PS1G831A(L)FP
t
t
RPST
QH
Q
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