hy5ps1g831alfp Hynix Semiconductor, hy5ps1g831alfp Datasheet - Page 4

• Manufacturer Part Number: hy5ps1g831alfp
• Description: 1gb Ddr2 Sdram
• Manufacturer: Hynix Semiconductor

Rev. 0.7 / Oct. 2007
Note:
XX* is the speed bin, refer to the Operation Frequency table for complete part number.
Hynix lead-free products are compliant to RoHS.
1. Description
Ordering Information
HY5PS1G1631A(L)FP-XX*
HY5PS1G431A(L)FP-XX*
HY5PS1G831A(L)FP-XX*
1.1 Device Features & Ordering Information
1.1.1 Key Features
• VDD=1.8V +/- 0.1V
• VDDQ=1.8 +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising
• Programmable CAS latency 3, 4 and 5 supported
• Programmable additive latency 0, 1, 2, 3 and 4supported
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Internal eight bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 68ball FBGA(x4/x8) , 92ball FBGA(x16)
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Read Data Strobe supported (x8 only)
• Self-Refresh High Temperature Entry
edges of the clock
Part No.
Configuration Package
256Mx4
128Mx8
64Mx16
68 Ball
92 Ball
Operating Frequency
Grade
E3
C4
Y5
tCK(ns)
3.75
5
3
CL
3
4
5
HY5PS1G1631A(L)FP
HY5PS1G431A(L)FP
HY5PS1G831A(L)FP
tRCD
3
4
5
tRP
3
4
5
Unit
Clk
Clk
Clk
4